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1.发明授权Semiconductor process and integrated circuit having dual metal oxide gate dielectric with single metal gate electrode 有权具有双金属氧化物栅极电介质和单金属栅电极的半导体工艺和集成电路公开(公告)号：US06897095B1
公开(公告)日：2005-05-24
申请号：US10843850
申请日：2004-05-12
IPC分类号： H01L21/8238
CPC分类号： H01L21/823857
摘要： A semiconductor fabrication process includes forming first and second transistors over first and second well regions, respectively where the first transistor has a first gate dielectric and the second transistor has a second gate dielectric different from the first gate dielectric. The first transistor has a first gate electrode and the second transistor has a second gate electrode. The first and second gate electrodes are the same in composition. The first gate dielectric and the second gate dielectric may both include high-K dielectrics such as Hafnium oxide and Aluminum oxide. The first and second gate electrodes both include a gate electrode layer overlying the respective gate dielectrics. The gate electrode layer is preferably either TaSiN and TaC. The first and second gate electrodes may both include a conductive layer overlying the gate electrode layer. In one such embodiment, the conductive layer may include polysilicon and tungsten.
摘要翻译： 半导体制造工艺包括在第一和第二阱区域分别形成第一和第二晶体管，其中第一晶体管具有第一栅极电介质，而第二晶体管具有不同于第一栅极电介质的第二栅极电介质。 第一晶体管具有第一栅电极，第二晶体管具有第二栅电极。 第一和第二栅电极的组成相同。 第一栅极电介质和第二栅极电介质可以都包括高K电介质，例如氧化铪和氧化铝。 第一和第二栅电极都包括覆盖各个栅极电介质的栅极电极层。 栅电极层优选为TaSiN和TaC。 第一和第二栅电极都可以包括覆盖栅电极层的导电层。 在一个这样的实施例中，导电层可以包括多晶硅和钨。
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公开(公告)号：US06790719B1
公开(公告)日：2004-09-14
申请号：US10410043
申请日：2003-04-09
IPC分类号： H01L21337
CPC分类号： H01L21/823468 , H01L21/82345 , H01L21/823462
摘要： A semiconductor device has a P channel gate stack comprising a first metal type and a second metal type over the first metal type and an N channel gate stack comprising the second metal type in direct contact with the a gate dielectric. The N channel gate stack and a portion of the P channel gate stack are etched by a dry etch. The etch of P channel gate stack is completed with a wet etch. The wet etch is very selective to the gate dielectric and to the second metal type so that the N channel transistor is not adversely effected by completing the etch of the P channel gate stack.
摘要翻译： 半导体器件具有包括第一金属类型的第一金属类型和第二金属类型的P沟道栅极堆叠以及包括与栅极电介质直接接触的第二金属类型的N沟道栅极堆叠。 通过干蚀刻来蚀刻N沟道栅极堆叠和P沟道栅极堆叠的一部分。 通过湿式蚀刻完成P沟道栅叠层的蚀刻。 湿蚀刻对栅极电介质和第二金属类型是非常选择的，使得N沟道晶体管不会通过完成P沟道栅极堆叠的蚀刻而受到不利影响。
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公开(公告)号：US06320784B1
公开(公告)日：2001-11-20
申请号：US09524916
申请日：2000-03-14
申请人： Ramachandran Muralidhar , Sucharita Madhukar , Bo Jiang , Bruce E. White , Srikanth B. Samavedam , David L. O'Meara , Michael Alan Sadd
发明人： Ramachandran Muralidhar , Sucharita Madhukar , Bo Jiang , Bruce E. White , Srikanth B. Samavedam , David L. O'Meara , Michael Alan Sadd
IPC分类号： G11C1100
CPC分类号： B82Y10/00 , G11C11/56 , G11C11/5671 , G11C16/0416 , G11C2216/08 , H01L29/7887 , H01L29/7888
摘要： A memory cell (101), its method of formation, and operation are disclosed. In accordance with one embodiment, the memory cell (101) comprises a first and second current carrying electrode (12) a control electrode (19), and doped discontinuous storage elements (17). In accordance with an alternative embodiment, memory cell programming is accomplished by removing or adding an average of approximately at least a first charge (30, 62, 64), which can be electron(s) or hole(s) from each of the doped discontinuous storage elements (17).
摘要翻译： 公开了一种存储单元（101），其形成方法和操作。 根据一个实施例，存储单元（101）包括第一和第二载流电极（12），控制电极（19）和掺杂的非连续存储元件（17）。 根据替代实施例，存储器单元编程通过去除或添加大约至少第一电荷（30,62,64）的平均值来实现，所述第一电荷可以是来自掺杂的每一个的电子或空穴 不连续存储元件（17）。
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公开(公告)号：US20130249015A1
公开(公告)日：2013-09-26
申请号：US13893026
申请日：2013-05-13
IPC分类号： H01L27/092
CPC分类号： H01L27/092 , H01L21/823807 , H01L21/823857 , H01L29/1054
摘要： An integrated circuit with devices having dielectric layers with different thicknesses. The dielectric layers include a high-k dielectric and some of the dielectric layers include an oxide layer that is formed from an oxidation process. Each device includes a layer including germanium or carbon located underneath the electrode stack of the device. A silicon cap layers is located over the layer including germanium or carbon.
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公开(公告)号：US08178401B2
公开(公告)日：2012-05-15
申请号：US11530058
申请日：2006-09-08
IPC分类号： H01L21/8238
CPC分类号： H01L21/823842
摘要： A method of fabricating a MOS transistor that comprises a dual-metal gate that is formed from heterotypical metals. A gate dielectric (34), such as HfO2, is deposited on a semiconductor substrate. A sacrificial layer (35), is next deposited over the gate dielectric. The sacrificial layer is patterned so that the gate dielectric over a first (pMOS, for example) area (32) of the substrate is exposed and gate dielectric over a second (nMOS, for example) area (33) of the substrate continues to be protected by the sacrificial layer. A first gate conductor material (51) is deposited over the remaining sacrificial area and over the exposed gate dielectric. The first gate conductor material is patterned so that first gate conductor material over the second area of the substrate is etched away. The sacrificial layer over the second area prevents damage to the underlying dielectric material as the first gate conductor material is removed.
摘要翻译： 一种制造包括由异型金属形成的双金属栅极的MOS晶体管的方法。 诸如HfO 2的栅极电介质（34）沉积在半导体衬底上。 牺牲层（35）接着沉积在栅极电介质上。 牺牲层被图案化，使得衬底的第一（pMOS，例如）区域（32）上的栅极电介质被暴露，并且衬底的第二（nMOS，例如）区域（33）上的栅极电介质继续是 受牺牲层保护。 第一栅极导体材料（51）沉积在剩余的牺牲区域上并暴露在栅极电介质上。 图案化第一栅极导体材料，使得衬底的第二区域上方的第一栅极导体材料被蚀刻掉。 第二区域上的牺牲层防止在去除第一栅极导体材料时损坏下面的介电材料。
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6.发明授权Process for forming an electronic device including a transistor having a metal gate electrode 失效用于形成包括具有金属栅电极的晶体管的电子器件的工艺公开(公告)号：US07750374B2
公开(公告)日：2010-07-06
申请号：US11559633
申请日：2006-11-14
IPC分类号： H01L29/78
CPC分类号： H01L21/823842 , H01L21/823807 , H01L29/1054
摘要： An electronic device includes an n-channel transistor and a p-channel transistor. The p-channel transistor has a first gate electrode with a first work function and a first channel region including a semiconductor layer immediately adjacent to a semiconductor substrate. In one embodiment, the first work function is less than the valence band of the semiconductor layer. In another embodiment, the n-channel transistor has a second gate electrode with a second work function different from the first work function and closer to a conduction band than a valence band of a second channel region. A process of forming the electronic device includes forming first and second gate electrodes having first and second work functions, respectively. First and second channel regions having a same minority carrier type are associated with the first and second gate electrodes, respectively.
摘要翻译： 电子器件包括n沟道晶体管和p沟道晶体管。 p沟道晶体管具有第一功函数的第一栅电极和包括与半导体衬底紧邻的半导体层的第一沟道区。 在一个实施例中，第一功函数小于半导体层的价带。 在另一个实施例中，n沟道晶体管具有第二栅极，其具有与第一功函数不同的第二功函数，并且比第二沟道区的价带更接近导带。 形成电子器件的工艺包括分别形成具有第一和第二功函数的第一和第二栅电极。 具有相同少数载流子类型的第一和第二沟道区分别与第一和第二栅电极相关联。
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公开(公告)号：US20090108296A1
公开(公告)日：2009-04-30
申请号：US11931565
申请日：2007-10-31
IPC分类号： H01L27/088 , H01L21/8234
CPC分类号： H01L27/092 , H01L21/823807 , H01L21/823857 , H01L29/1054
摘要： An integrated circuit with devices having dielectric layers with different thicknesses. The dielectric layers include a high-k dielectric and some of the dielectric layers include an oxide layer that is formed from an oxidation process. Each device includes a layer including germanium or carbon located underneath the electrode stack of the device. A silicon cap layers is located over the layer including germanium or carbon.
摘要翻译： 具有具有不同厚度的电介质层的器件的集成电路。 电介质层包括高k电介质，并且一些电介质层包括由氧化工艺形成的氧化物层。 每个器件包括位于器件的电极堆叠下方的包含锗或碳的层。 硅层位于包含锗或碳的层之上。
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8.发明授权Method of forming a semiconductor device having an interlayer and structure therefor 有权形成具有中间层的半导体器件及其结构的方法公开(公告)号：US07445976B2
公开(公告)日：2008-11-04
申请号：US11420525
申请日：2006-05-26
IPC分类号： H01L21/00
CPC分类号： H01L21/823857 , H01L21/82345 , H01L21/823462 , H01L21/823842 , H01L29/4966 , H01L29/517
摘要： A stack located over a substrate. The stack includes a layer between a dielectric layer and a metal layer. The layer includes a halogen and a metal. In one embodiment, the halogen is fluorine. In one embodiment, the stack is a control electrode stack for a transistor. In one example the control electrode stack is a gate stack for a MOSFET. In one example, the layer includes aluminum fluoride.
摘要翻译： 位于衬底上方的堆叠。 堆叠包括介电层和金属层之间的层。 该层包括卤素和金属。 在一个实施方案中，卤素是氟。 在一个实施例中，堆叠是用于晶体管的控制电极堆叠。 在一个示例中，控制电极堆叠是用于MOSFET的栅极堆叠。 在一个实例中，该层包括氟化铝。
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公开(公告)号：US09362280B2
公开(公告)日：2016-06-07
申请号：US13893026
申请日：2013-05-13
IPC分类号： H01L21/70 , H01L27/092 , H01L21/8238 , H01L29/10
CPC分类号： H01L27/092 , H01L21/823807 , H01L21/823857 , H01L29/1054
摘要： An integrated circuit with devices having dielectric layers with different thicknesses. The dielectric layers include a high-k dielectric and some of the dielectric layers include an oxide layer that is formed from an oxidation process. Each device includes a layer including germanium or carbon located underneath the electrode stack of the device. A silicon cap layers is located over the layer including germanium or carbon.
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公开(公告)号：US08460996B2
公开(公告)日：2013-06-11
申请号：US11931565
申请日：2007-10-31
IPC分类号： H01L21/8242
CPC分类号： H01L27/092 , H01L21/823807 , H01L21/823857 , H01L29/1054
摘要： An integrated circuit with devices having dielectric layers with different thicknesses. The dielectric layers include a high-k dielectric and some of the dielectric layers include an oxide layer that is formed from an oxidation process. Each device includes a layer including germanium or carbon located underneath the electrode stack of the device. A silicon cap layers is located over the layer including germanium or carbon.
摘要翻译： 具有具有不同厚度的电介质层的器件的集成电路。 电介质层包括高k电介质，并且一些电介质层包括由氧化工艺形成的氧化物层。 每个器件包括位于器件的电极堆叠下方的包含锗或碳的层。 硅层位于包含锗或碳的层之上。
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