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    Systems and methods for memory module power management
    1.
    发明授权
    Systems and methods for memory module power management 失效
    内存模块电源管理的系统和方法

    公开(公告)号：US07587559B2

    公开(公告)日：2009-09-08

    申请号：US11463743

    申请日：2006-08-10

    申请人： Mark A. Brittain ,  Warren E. Maule ,  Karthick Rajamani ,  Eric E. Retter ,  Robert B. Tremaine

    发明人： Mark A. Brittain ,  Warren E. Maule ,  Karthick Rajamani ,  Eric E. Retter ,  Robert B. Tremaine

    IPC分类号： G06F12/00

    CPC分类号： G11C5/143 ,  G06F1/3225 ,  G11C5/04 ,  G11C5/14 ,  G11C11/4072

    摘要： Systems and methods for determining memory module power requirements in a memory system. Embodiments include a memory system with a physical memory and a memory controller. The physical memory includes a plurality of memory devices. The memory controller is in communication with the physical memory and has a logical memory for storing power usage characteristics associated with the physical memory. The power usage characteristics are generated in response to a current operating environment of the memory system.

    摘要翻译： 用于确定存储器系统中的存储器模块功率需求的系统和方法。 实施例包括具有物理存储器和存储器控制器的存储器系统。 物理存储器包括多个存储器件。 存储器控制器与物理存储器通信，并且具有用于存储与物理存储器相关联的功率使用特性的逻辑存储器。 响应于存储器系统的当前操作环境而产生功率使用特性。

    SYSTEMS AND METHODS FOR MEMORY MODULE POWER MANAGEMENT
    2.
    发明申请
    SYSTEMS AND METHODS FOR MEMORY MODULE POWER MANAGEMENT 失效
    用于存储器模块电源管理的系统和方法

    公开(公告)号：US20080040563A1

    公开(公告)日：2008-02-14

    申请号：US11463743

    申请日：2006-08-10

    申请人： Mark A. Brittain ,  Warren E. Maule ,  Karthick Rajamani ,  Eric E. Retter ,  Robert B. Tremaine

    发明人： Mark A. Brittain ,  Warren E. Maule ,  Karthick Rajamani ,  Eric E. Retter ,  Robert B. Tremaine

    IPC分类号： G06F13/00 ,  G06F1/32

    CPC分类号： G11C5/143 ,  G06F1/3225 ,  G11C5/04 ,  G11C5/14 ,  G11C11/4072

    摘要： Systems and methods for determining memory module power requirements in a memory system. Embodiments include a memory system with a physical memory and a memory controller. The physical memory includes a plurality of memory devices. The memory controller is in communication with the physical memory and has a logical memory for storing power usage characteristics associated with the physical memory. The power usage characteristics are generated in response to a current operating environment of the memory system.

    摘要翻译： 用于确定存储器系统中的存储器模块功率需求的系统和方法。 实施例包括具有物理存储器和存储器控制器的存储器系统。 物理存储器包括多个存储器件。 存储器控制器与物理存储器通信，并且具有用于存储与物理存储器相关联的功率使用特性的逻辑存储器。 响应于存储器系统的当前操作环境而产生功率使用特性。

    Performing arithmetic operations using both large and small floating point values
    4.
    发明授权
    Performing arithmetic operations using both large and small floating point values 有权
    使用大和小浮点值执行算术运算

    公开(公告)号：US08909690B2

    公开(公告)日：2014-12-09

    申请号：US13324025

    申请日：2011-12-13

    申请人： John B. Carter ,  Bruce G. Mealey ,  Karthick Rajamani ,  Eric E. Retter ,  Jeffrey A. Stuecheli

    发明人： John B. Carter ,  Bruce G. Mealey ,  Karthick Rajamani ,  Eric E. Retter ,  Jeffrey A. Stuecheli

    IPC分类号： G06F7/38

    CPC分类号： G06F7/483 ,  G06F2207/382

    摘要： Mechanisms are provided for performing a floating point arithmetic operation in a data processing system. A plurality of floating point operands of the floating point arithmetic operation are received and bits in a mantissa of at least one floating point operand of the plurality of floating point operands are shifted. One or more bits of the mantissa that are shifted outside a range of bits of the mantissa of at least one floating point operand are stored and a vector value is generated based on the stored one or more bits of the mantissa that are shifted outside of the range of bits of the mantissa of the at least one floating point operand. A resultant value is generated for the floating point arithmetic operation based on the vector value and the plurality of floating point operands.

    摘要翻译： 提供了用于在数据处理系统中执行浮点算术运算的机构。 接收浮点算术运算的多个浮点操作数，并移位多个浮点操作数的至少一个浮点运算数的尾数中的位。 存储在至少一个浮点操作数的尾数的位的范围之外移动的尾数的一个或多个比特，并且基于所存储的一个或多个尾数位被生成向量值， 至少一个浮点操作数的尾数的位的范围。 基于向量值和多个浮点操作数，生成用于浮点运算的结果值。

    Performing arithmetic operations using both large and small floating point values
    8.
    发明授权
    Performing arithmetic operations using both large and small floating point values 有权
    使用大和小浮点值执行算术运算

    公开(公告)号：US08984041B2

    公开(公告)日：2015-03-17

    申请号：US13598847

    申请日：2012-08-30

    申请人： John B. Carter ,  Bruce G. Mealey ,  Karthick Rajamani ,  Eric E. Retter ,  Jeffrey A. Stuecheli

    发明人： John B. Carter ,  Bruce G. Mealey ,  Karthick Rajamani ,  Eric E. Retter ,  Jeffrey A. Stuecheli

    IPC分类号： G06F7/38 ,  G06F7/483

    CPC分类号： G06F7/483 ,  G06F2207/382

    摘要： Mechanisms are provided for performing a floating point arithmetic operation in a data processing system. A plurality of floating point operands of the floating point arithmetic operation are received and bits in a mantissa of at least one floating point operand of the plurality of floating point operands are shifted. One or more bits of the mantissa that are shifted outside a range of bits of the mantissa of at least one floating point operand are stored and a vector value is generated based on the stored one or more bits of the mantissa that are shifted outside of the range of bits of the mantissa of the at least one floating point operand. A resultant value is generated for the floating point arithmetic operation based on the vector value and the plurality of floating point operands.

    摘要翻译： 提供了用于在数据处理系统中执行浮点算术运算的机构。 接收浮点算术运算的多个浮点操作数，并移位多个浮点操作数的至少一个浮点运算数的尾数中的位。 存储在至少一个浮点操作数的尾数的位的范围之外移动的尾数的一个或多个比特，并且基于所存储的一个或多个尾数位被生成向量值， 至少一个浮点操作数的尾数的位的范围。 基于向量值和多个浮点操作数，生成用于浮点运算的结果值。

    SYNCHRONIZED COMMAND THROTTLING FOR MULTI-CHANNEL DUTY-CYCLE BASED MEMORY POWER MANAGEMENT
    9.
    发明申请
    SYNCHRONIZED COMMAND THROTTLING FOR MULTI-CHANNEL DUTY-CYCLE BASED MEMORY POWER MANAGEMENT 失效
    基于多通道占空比的存储器电源管理的同步指令脉宽调制

    公开(公告)号：US20130151867A1

    公开(公告)日：2013-06-13

    申请号：US13314379

    申请日：2011-12-08

    申请人： John S. Dodson ,  Karthick Rajamani ,  Eric E. Retter ,  Kenneth L. Wright

    发明人： John S. Dodson ,  Karthick Rajamani ,  Eric E. Retter ,  Kenneth L. Wright

    IPC分类号： G06F1/26 ,  G06F12/00

    CPC分类号： G06F3/0644 ,  G06F1/32 ,  G06F1/3206 ,  G06F1/3275 ,  G06F13/16 ,  G11C5/147 ,  G11C11/4074 ,  Y02D10/14

    摘要： A technique for memory command throttling in a partitioned memory subsystem includes accepting, by a master memory controller included in multiple memory controllers, a synchronization command. The synchronization command includes command data that includes an associated synchronization indication (e.g., a synchronization bit or bits) for each of the multiple memory controllers and each of the multiple memory controllers controls a respective partition of the partitioned memory subsystem. In response to receiving the synchronization command, the master memory controller forwards the synchronization command to the multiple memory controllers. In response to receiving the forwarded synchronization command each of the multiple memory controllers de-asserts an associated status bit. In response to receiving the forwarded synchronization command, each of the multiple memory controllers determines whether the associated synchronization indication is asserted. Each of the multiple memory controllers with the asserted associated synchronization indication then transmits the forwarded synchronization command to associated power control logic.

    摘要翻译： 在分区存储器子系统中用于存储器命令调节的技术包括由包含在多个存储器控制器中的主存储器控制器接受同步命令。 同步命令包括命令数据，其包括用于多个存储器控制器中的每一个的相关联的同步指示（例如，同步位或位），并且多个存储器控制器中的每一个控制分区存储器子系统的相应分区。 响应于接收到同步命令，主存储器控制器将同步命令转发到多个存储器控制器。 响应于接收到转发的同步命令，多个存储器控制器中的每个存储器控制器断言相关联的状态位。 响应于接收到转发的同步命令，多个存储器控制器中的每一个确定相关联的同步指示是否被断言。 具有断言的相关同步指示的多个存储器控制器中的每一个然后将转发的同步命令发送到相关联的功率控制逻辑。