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公开(公告)号：US20080040563A1
公开(公告)日：2008-02-14
申请号：US11463743
申请日：2006-08-10
CPC分类号： G11C5/143 , G06F1/3225 , G11C5/04 , G11C5/14 , G11C11/4072
摘要： Systems and methods for determining memory module power requirements in a memory system. Embodiments include a memory system with a physical memory and a memory controller. The physical memory includes a plurality of memory devices. The memory controller is in communication with the physical memory and has a logical memory for storing power usage characteristics associated with the physical memory. The power usage characteristics are generated in response to a current operating environment of the memory system.
摘要翻译： 用于确定存储器系统中的存储器模块功率需求的系统和方法。 实施例包括具有物理存储器和存储器控制器的存储器系统。 物理存储器包括多个存储器件。 存储器控制器与物理存储器通信，并且具有用于存储与物理存储器相关联的功率使用特性的逻辑存储器。 响应于存储器系统的当前操作环境而产生功率使用特性。
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公开(公告)号：US07587559B2
公开(公告)日：2009-09-08
申请号：US11463743
申请日：2006-08-10
IPC分类号： G06F12/00
CPC分类号： G11C5/143 , G06F1/3225 , G11C5/04 , G11C5/14 , G11C11/4072
摘要： Systems and methods for determining memory module power requirements in a memory system. Embodiments include a memory system with a physical memory and a memory controller. The physical memory includes a plurality of memory devices. The memory controller is in communication with the physical memory and has a logical memory for storing power usage characteristics associated with the physical memory. The power usage characteristics are generated in response to a current operating environment of the memory system.
摘要翻译： 用于确定存储器系统中的存储器模块功率需求的系统和方法。 实施例包括具有物理存储器和存储器控制器的存储器系统。 物理存储器包括多个存储器件。 存储器控制器与物理存储器通信，并且具有用于存储与物理存储器相关联的功率使用特性的逻辑存储器。 响应于存储器系统的当前操作环境而产生功率使用特性。
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公开(公告)号：US20130151578A1
公开(公告)日：2013-06-13
申请号：US13598847
申请日：2012-08-30
CPC分类号： G06F7/483 , G06F2207/382
摘要： Mechanisms are provided for performing a floating point arithmetic operation in a data processing system. A plurality of floating point operands of the floating point arithmetic operation are received and bits in a mantissa of at least one floating point operand of the plurality of floating point operands are shifted. One or more bits of the mantissa that are shifted outside a range of bits of the mantissa of at least one floating point operand are stored and a vector value is generated based on the stored one or more bits of the mantissa that are shifted outside of the range of bits of the mantissa of the at least one floating point operand. A resultant value is generated for the floating point arithmetic operation based on the vector value and the plurality of floating point operands.
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4.发明授权公开(公告)号：US08984041B2
公开(公告)日：2015-03-17
申请号：US13598847
申请日：2012-08-30
CPC分类号： G06F7/483 , G06F2207/382
摘要： Mechanisms are provided for performing a floating point arithmetic operation in a data processing system. A plurality of floating point operands of the floating point arithmetic operation are received and bits in a mantissa of at least one floating point operand of the plurality of floating point operands are shifted. One or more bits of the mantissa that are shifted outside a range of bits of the mantissa of at least one floating point operand are stored and a vector value is generated based on the stored one or more bits of the mantissa that are shifted outside of the range of bits of the mantissa of the at least one floating point operand. A resultant value is generated for the floating point arithmetic operation based on the vector value and the plurality of floating point operands.
摘要翻译： 提供了用于在数据处理系统中执行浮点算术运算的机构。 接收浮点算术运算的多个浮点操作数，并移位多个浮点操作数的至少一个浮点运算数的尾数中的位。 存储在至少一个浮点操作数的尾数的位的范围之外移动的尾数的一个或多个比特，并且基于所存储的一个或多个尾数位被生成向量值， 至少一个浮点操作数的尾数的位的范围。 基于向量值和多个浮点操作数，生成用于浮点运算的结果值。
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5.发明申请SYNCHRONIZED COMMAND THROTTLING FOR MULTI-CHANNEL DUTY-CYCLE BASED MEMORY POWER MANAGEMENT 失效基于多通道占空比的存储器电源管理的同步指令脉宽调制公开(公告)号：US20130151867A1
公开(公告)日：2013-06-13
申请号：US13314379
申请日：2011-12-08
CPC分类号： G06F3/0644 , G06F1/32 , G06F1/3206 , G06F1/3275 , G06F13/16 , G11C5/147 , G11C11/4074 , Y02D10/14
摘要： A technique for memory command throttling in a partitioned memory subsystem includes accepting, by a master memory controller included in multiple memory controllers, a synchronization command. The synchronization command includes command data that includes an associated synchronization indication (e.g., a synchronization bit or bits) for each of the multiple memory controllers and each of the multiple memory controllers controls a respective partition of the partitioned memory subsystem. In response to receiving the synchronization command, the master memory controller forwards the synchronization command to the multiple memory controllers. In response to receiving the forwarded synchronization command each of the multiple memory controllers de-asserts an associated status bit. In response to receiving the forwarded synchronization command, each of the multiple memory controllers determines whether the associated synchronization indication is asserted. Each of the multiple memory controllers with the asserted associated synchronization indication then transmits the forwarded synchronization command to associated power control logic.
摘要翻译： 在分区存储器子系统中用于存储器命令调节的技术包括由包含在多个存储器控制器中的主存储器控制器接受同步命令。 同步命令包括命令数据，其包括用于多个存储器控制器中的每一个的相关联的同步指示（例如，同步位或位），并且多个存储器控制器中的每一个控制分区存储器子系统的相应分区。 响应于接收到同步命令，主存储器控制器将同步命令转发到多个存储器控制器。 响应于接收到转发的同步命令，多个存储器控制器中的每个存储器控制器断言相关联的状态位。 响应于接收到转发的同步命令，多个存储器控制器中的每一个确定相关联的同步指示是否被断言。 具有断言的相关同步指示的多个存储器控制器中的每一个然后将转发的同步命令发送到相关联的功率控制逻辑。
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6.发明授权公开(公告)号：US08909690B2
公开(公告)日：2014-12-09
申请号：US13324025
申请日：2011-12-13
IPC分类号： G06F7/38
CPC分类号： G06F7/483 , G06F2207/382
摘要： Mechanisms are provided for performing a floating point arithmetic operation in a data processing system. A plurality of floating point operands of the floating point arithmetic operation are received and bits in a mantissa of at least one floating point operand of the plurality of floating point operands are shifted. One or more bits of the mantissa that are shifted outside a range of bits of the mantissa of at least one floating point operand are stored and a vector value is generated based on the stored one or more bits of the mantissa that are shifted outside of the range of bits of the mantissa of the at least one floating point operand. A resultant value is generated for the floating point arithmetic operation based on the vector value and the plurality of floating point operands.
摘要翻译： 提供了用于在数据处理系统中执行浮点算术运算的机构。 接收浮点算术运算的多个浮点操作数，并移位多个浮点操作数的至少一个浮点运算数的尾数中的位。 存储在至少一个浮点操作数的尾数的位的范围之外移动的尾数的一个或多个比特，并且基于所存储的一个或多个尾数位被生成向量值， 至少一个浮点操作数的尾数的位的范围。 基于向量值和多个浮点操作数，生成用于浮点运算的结果值。
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公开(公告)号：US20130151577A1
公开(公告)日：2013-06-13
申请号：US13324025
申请日：2011-12-13
CPC分类号： G06F7/483 , G06F2207/382
摘要： Mechanisms are provided for performing a floating point arithmetic operation in a data processing system. A plurality of floating point operands of the floating point arithmetic operation are received and bits in a mantissa of at least one floating point operand of the plurality of floating point operands are shifted. One or more bits of the mantissa that are shifted outside a range of bits of the mantissa of at least one floating point operand are stored and a vector value is generated based on the stored one or more bits of the mantissa that are shifted outside of the range of bits of the mantissa of the at least one floating point operand. A resultant value is generated for the floating point arithmetic operation based on the vector value and the plurality of floating point operands.
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公开(公告)号：US09329670B2
公开(公告)日：2016-05-03
申请号：US13488822
申请日：2012-06-05
申请人： Malcolm S. Allen-Ware , Wei Huang , Fadi M. Kassem , Karthick Rajamani , Todd J. Rosedahl , Guillermo J. Silva
发明人： Malcolm S. Allen-Ware , Wei Huang , Fadi M. Kassem , Karthick Rajamani , Todd J. Rosedahl , Guillermo J. Silva
摘要： A mechanism is provided for estimating energy/power consumption of a fixed-frequency operating mode while system is running in dynamic power management mode. For each time interval in a plurality of time intervals within a time period: a first processor identifies a modeled total nominal power value for at least one second processor during a current time interval, stores the modeled total nominal power value for the current time interval in a storage, identifies a dynamic power management mode power value for the at least one second processor in the data processing system during the current interval, and stores the dynamic power management mode power value for the current time interval in the storage. Responsive to the time period expiring, a comparison is produced of a plurality of modeled total nominal power values and a plurality of dynamic power management mode power values over the time period.
摘要翻译： 提供了一种用于在系统以动态功率管理模式运行时估计固定频率操作模式的能量/功率消耗的机制。 对于在一段时间段内的多个时间间隔中的每个时间间隔：第一处理器在当前时间间隔期间识别至少一个第二处理器的建模总额定功率值，将建模的总额定功率值存储在当前时间间隔中 存储器，在当前间隔期间识别数据处理系统中的至少一个第二处理器的动态功率管理模式功率值，并将当前时间间隔的动态功率管理模式功率值存储在存储器中。 响应于时间段到期，在该时间段内产生多个建模的总额定功率值和多个动态功率管理模式功率值的比较。
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公开(公告)号：US08719527B2
公开(公告)日：2014-05-06
申请号：US13460044
申请日：2012-04-30
IPC分类号： G06F12/06
CPC分类号： G06F12/08 , G06F1/3275 , G06F9/5094 , G06F2212/1028 , G11C5/04 , Y02D10/13 , Y02D10/14 , Y02D10/22
摘要： A method for increasing a capacity of a memory is provided in the illustrative embodiments. Using an application executing using a processor wherein the memory includes a set of ranks, the memory is configured to form a cold tier and a hot tier, the cold tier including a first subset of ranks from the set of ranks in the memory, and the hot tier including a second subset of ranks from the set of ranks in the memory. A determination is made whether a page to which a memory access request is directed is located in the cold tier in the memory. In response to the page being located in the cold tier of the memory, the processing of the memory access request is throttled by processing the memory access request with a delay.
摘要翻译： 在说明性实施例中提供了用于增加存储器的容量的方法。 使用使用处理器执行的应用程序，其中所述存储器包括一组等级，所述存储器被配置为形成冷层和热层，所述冷层包括来自所述存储器中的所述一组等级的第一子群， 热层包括来自内存中的一组排名的第二个子集。 确定存储器访问请求所指向的页面是否位于存储器中的冷层中。 响应于页面位于存储器的冷层中，通过以延迟处理存储器访问请求来限制存储器访问请求的处理。
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10.发明授权公开(公告)号：US08635381B2
公开(公告)日：2014-01-21
申请号：US12869591
申请日：2010-08-26
IPC分类号： G06F3/00
CPC分类号： G06F11/3485 , G06F2201/88
摘要： According to one aspect of the present disclosure a method and technique for monitoring memory access is disclosed. The method includes monitoring, by a plurality of memory controllers, access to a memory unit, wherein each memory controller is associated with a different range of memory addresses of the memory unit, and wherein each memory controller monitors access for its associated range of memory addresses. The method also includes updating an incrementor with access data corresponding to accesses to the memory unit, wherein each memory controller updates the access data based on access of its associated range of memory addresses. The method further includes storing, by each respective memory controller, the updated access data in a cache corresponding to the respective range of memory addresses and, responsive to the updated access data for a respective range of memory addresses exceeding a threshold, storing the access data for the respective range of memory addresses in memory unit.
摘要翻译： 根据本公开的一个方面，公开了一种用于监视存储器访问的方法和技术。 该方法包括通过多个存储器控制器监视对存储器单元的访问，其中每个存储器控制器与存储器单元的存储器地址的不同范围相关联，并且其中每个存储器控制器监视对其相关联的存储器地址范围的访问 。 该方法还包括使用与对存储器单元的访问相对应的访问数据来更新增量器，其中每个存储器控制器基于其相关联的存储器地址范围的访问来更新访问数据。 该方法还包括由每个相应的存储器控制器将更新的访问数据存储在与存储器地址的相应范围相对应的高速缓存中，并且响应于对于超过阈值的存储器地址的相应范围的更新的访问数据，存储访问数据 对于存储器单元中的各个存储器地址范围。
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