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    Acoustic noise mitigation using periodicity disruption
    5.
    发明授权
    Acoustic noise mitigation using periodicity disruption 有权
    使用周期性破坏的声学噪声减轻

    公开(公告)号：US09444328B2

    公开(公告)日：2016-09-13

    申请号：US13532949

    申请日：2012-06-26

    申请人： Jessica Gullbrand ,  Karthik Sankaranarayanan ,  Willem M. Beltman ,  Eric Baugh ,  Stephen H. Gunther ,  Jay D. Schwartz

    发明人： Jessica Gullbrand ,  Karthik Sankaranarayanan ,  Willem M. Beltman ,  Eric Baugh ,  Stephen H. Gunther ,  Jay D. Schwartz

    IPC分类号： G06F1/26 ,  H02M1/44 ,  H02M1/36 ,  G06F1/32

    CPC分类号： H02M1/44 ,  G06F1/3203 ,  H02M1/36

    摘要： In one or more embodiments, a fixed time interval for a system is determined. The fixed time interval corresponds to time between clock ticks. A random time interval is determined based on the fixed time interval and an offset. One or more electronic components affixed to a motherboard are transitioned to a new power state when the random time interval has elapsed. By introducing a randomization to the timing element to a control signal that drives the power state transition, a periodicity for the system is disrupted. The disruption in periodicity mitigates acoustic noise generated by vibrations in electronic components and motherboards affected by current and/or voltage transitions.

    摘要翻译： 在一个或多个实施例中，确定系统的固定时间间隔。 固定时间间隔对应于时钟间隔之间的时间。 基于固定时间间隔和偏移确定随机时间间隔。 当随机时间间隔过去时，固定到母板上的一个或多个电子部件转变到新的电源状态。 通过将定时元件的随机化引入到驱动电源状态转换的控制信号，系统的周期性被破坏。 周期性的破坏减轻了受电流和/或电压转换影响的电子元件和母板振动产生的声音噪声。

    Method, apparatus, and system for energy efficiency and energy conservation including detecting and controlling current ramps in processing circuit
    6.
    发明授权
    Method, apparatus, and system for energy efficiency and energy conservation including detecting and controlling current ramps in processing circuit 有权
    能量效率和节能的方法，装置和系统，包括检测和控制处理电路中的电流斜坡

    公开(公告)号：US09134788B2

    公开(公告)日：2015-09-15

    申请号：US13340511

    申请日：2011-12-29

    申请人： Anupama Suryanarayanan ,  Matthew C. Merten ,  Ryan L. Carlson ,  Stephen H. Gunther

    发明人： Anupama Suryanarayanan ,  Matthew C. Merten ,  Ryan L. Carlson ,  Stephen H. Gunther

    IPC分类号： G06F1/32

    CPC分类号： G06F1/3243 ,  Y02D10/152

    摘要： Some implementations provide techniques and arrangements for adjusting a rate at which operations are performed by a processor based on a comparison of a first indication of power consumed by the processor as a result of performing a first set of operations and a second indication of power consumed by the processor as a result of performing a second set of operations. The rate at which operations are performed by the processor may be adjusted when the comparison indicates that a difference between the first indication of power consumed by the processor and the second indication of power consumed by the processor is greater than a threshold value.

    摘要翻译： 一些实施方案提供了用于调整由处理器执行操作的速率的技术和布置，其基于由执行第一组操作的结果和由处理器消耗的功率的第二指示来比较由处理器消耗的功率的第一指示 作为执行第二组操作的结果的处理器。 当比较指示处理器消耗的功率的第一指示与处理器消耗的功率的第二指示之间的差异大于阈值时，可以调整由处理器执行操作的速率。

    Independent Control Of Processor Core Retention States
    8.
    发明申请
    Independent Control Of Processor Core Retention States 有权
    处理器核心保留状态的独立控制

    公开(公告)号：US20140189225A1

    公开(公告)日：2014-07-03

    申请号：US13729833

    申请日：2012-12-28

    申请人： Shaun M. Conrad ,  Stephen H. Gunther ,  Jeremy J. Shrall ,  Anant S. Deval ,  Sanjeev S. Jahagirdar

    发明人： Shaun M. Conrad ,  Stephen H. Gunther ,  Jeremy J. Shrall ,  Anant S. Deval ,  Sanjeev S. Jahagirdar

    IPC分类号： G06F1/32 ,  G11C7/10

    CPC分类号： G06F1/3296 ,  G06F1/3243 ,  Y02D10/152 ,  Y02D10/172

    摘要： In an embodiment, a processor includes a first processor core, a second processor core, a first voltage regulator to provide a first voltage to the first processor core with a first active value when the first processor core is active, and a second voltage regulator to provide a second voltage to the second processor core with a second active value when the second processor core is active. Responsive to a request to place the first processor core in a first low power state with an associated first low power voltage value, the first voltage regulator is to reduce the first voltage to a second low power voltage value that is less than the first low power voltage value, independent of the second voltage regulator. First data stored in a first register of the first processor core is retained at the second low power value. Other embodiments are described and claimed.

    摘要翻译： 在一个实施例中，处理器包括第一处理器核心，第二处理器核心，第一电压调节器，以在第一处理器核心活动时向第一处理器核心提供具有第一有效值的第一电压;以及第二电压调节器， 当第二处理器核心活动时，向第二处理器核心提供具有第二有效值的第二电压。 响应于将第一处理器核放置在具有相关联的第一低功率电压值的第一低功率状态的请求，第一电压调节器将第一电压降低到小于第一低功率电压的第二低功率电压值 电压值，独立于第二电压调节器。 存储在第一处理器核心的第一寄存器中的第一数据保持在第二低功率值。 描述和要求保护其他实施例。

    Controlling Configurable Peak Performance Limits Of A Processor
    9.
    发明申请
    Controlling Configurable Peak Performance Limits Of A Processor 有权
    控制处理器的可配置峰值性能限制

    公开(公告)号：US20140181538A1

    公开(公告)日：2014-06-26

    申请号：US13724732

    申请日：2012-12-21

    申请人： Jeremy J. Shrall ,  Stephen H. Gunther ,  Krishnakanth V. Sistla ,  Ryan D. Wells ,  Shaun M. Conrad

    发明人： Jeremy J. Shrall ,  Stephen H. Gunther ,  Krishnakanth V. Sistla ,  Ryan D. Wells ,  Shaun M. Conrad

    IPC分类号： G06F1/26

    CPC分类号： G06F1/3243 ,  G06F1/324 ,  G06F3/14 ,  Y02D10/152

    摘要： In one embodiment, the present invention includes a processor having a plurality of cores each to execute instructions, a non-volatile storage to store maximum peak operating frequency values each a function of a given number of active cores, a configuration storage to store frequency limits each corresponding to one of the maximum peak operating frequency values or a configurable clip frequency value less than the maximum peak operating frequency value. In turn, a power controller is configured to limit operating frequency of the cores to a corresponding frequency limit obtained from the configuration storage. Other embodiments are described and claimed.

    摘要翻译： 在一个实施例中，本发明包括具有多个核的处理器，每个核每个用于执行指令;非易失性存储器，用于存储最大峰值操作频率值，每一个是给定数量的活动核心的功能;存储频率限制的配置存储 每个对应于最大峰值工作频率值之一或可配置的剪辑频率值小于最大峰值工作频率值。 反过来，功率控制器被配置为将芯的操作频率限制到从配置存储获得的相应频率限制。 描述和要求保护其他实施例。