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公开(公告)号：US5654675A
公开(公告)日：1997-08-05
申请号：US611831
申请日：1996-03-06
CPC分类号： H03L7/0891 , H03L7/099 , H03L7/107 , H03L2207/04 , H03L7/0995
摘要： A fully integrated, phase locked loop (PLL) having improved jitter characteristics uses the same digital/analog converter (DAC) that is normally used to control the time constant of the low pass loop filter to control the value of a capacitance connected between the output of a voltage-to-current converting input stage of the voltage controlled oscillator and ground. The capacitance introduces a third pole in the loop's transfer function. In this way, the separation in the frequency domain between the zero and the third pole of the transfer function is kept constant; thus, the damping factor remains constant while the .omega..sub.0 of the PLL is varied.
摘要翻译： 具有改进的抖动特性的完全集成的锁相环（PLL）使用相同的数/模转换器（DAC），其通常用于控制低通环路滤波器的时间常数，以控制连接在输出端 压控振荡器和地的电压 - 电流转换输入级。 电容在循环传递函数中引入了第三极点。 以这种方式，传递函数的零和第三极之间的频域分离保持不变; 因此，阻尼因子保持恒定，同时PLL的ω0变化。
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2.发明授权
公开(公告)号：US5134481A
公开(公告)日：1992-07-28
申请号：US631915
申请日：1990-12-21
摘要： A method of automatically measuring the horizontal scan frequency of a composite synchronism signal, comprising horizontal synchronization impulses at line frequency, consists of first performing a count of a number of impulses having a repeat frequency higher than said line frequency, as intervening between two successive impulses at line frequency.The count value, corresponding to said number of impulses, is stored to obtain the line frequency of the signal, and thereafter, a series of down counts is effected, as initiated at predetermined times, until a change of frequency of the signal is detected.
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3.再颁专利Method of automatically measuring the horizontal scan frequency of a composite synchronism signal, and an electronic circuit operating in accordance with the method 失效一种自动测量复合同步信号的水平扫描频率的方法，以及根据该方法操作的电子电路
公开(公告)号：USRE36508E
公开(公告)日：2000-01-18
申请号：US932000
申请日：1997-09-17
摘要： A method of automatically measuring the horizontal scan frequency of a composite synchronism signal, comprising horizontal synchronization impulses at line frequency, consists of first performing a count of a number of impulses having a repeat frequency higher than said line frequency, as intervening between two successive impulses at line frequency.The count value, corresponding to said number of impulses, is stored to obtain the line frequency of the signal, and thereafter, a series of down counts is effected, as initiated at predetermined times, until a change of frequency of the signal is detected.
摘要翻译： 一种自动测量复合同步信号的水平扫描频率的方法，包括在线频率处的水平同步脉冲，包括首先执行具有高于所述线频率的重复频率的多个脉冲的计数，作为介于两个连续脉冲之间 在线频率。 存储对应于所述脉冲数的计数值以获得信号的线路频率，然后在预定时间开始进行一系列递减计数，直到检测到信号的频率变化。
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公开(公告)号：US5621358A
公开(公告)日：1997-04-15
申请号：US454924
申请日：1995-05-31
CPC分类号： H03F3/45883 , H03F3/45286 , H03F3/45807 , H03G1/0023 , H03F2203/45648
摘要： A controlled gain transconductor (20) which comprises a transconductance stage (3) having at least two input terminals (I1, I2) and at least two output terminals (O1, O2), an active load (4) connected to the output terminals of the transconductance stage and a control circuit (5) for the active load (4) connected between said output terminals (O1, O2) and the active load (4).Also provided is a circuit portion (10) being a replica of the transconductance stage (3), the active load (4) and the control circuit (5). This replicated portion (10) has an output connected to the control circuit (5) of the transconductor (20) to provide a predetermined voltage value (Vc) required for adjusting the DC gain of the device.
摘要翻译： 包括具有至少两个输入端（I1，I2）和至少两个输出端（O1，O2）的跨导级（3）的受控增益跨导体（20），连接到 跨导级和连接在所述输出端子（O1，O2）和有源负载（4）之间的有源负载（4）的控制电路（5）。 还提供了作为跨导级（3），有源负载（4）和控制电路（5）的复制品的电路部分（10）。 该复制部分（10）具有连接到跨导体（20）的控制电路（5）的输出，以提供调整装置的DC增益所需的预定电压值（Vc）。
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公开(公告)号：US5332937A
公开(公告)日：1994-07-26
申请号：US942678
申请日：1992-09-09
CPC分类号： H03F3/45179 , H03F3/45286 , H03F2203/45024 , H03H11/0433
摘要： A transconductor differential stage for high-frequency filters, which has a MOS differential input pair with common sources. The drain of each MOS input is connected to the emitter of an npn bipolar. These two matched bipolars have their gates connected together with the gate of a third bipolar, which is diode-connected. Two matched current sources feed the two bipolars, and a third current source feeds the third bipolar. A single controlled current sink is connected to the sources of both MOS input transistors, and also (through a resistor) to the third bipolar.
摘要翻译： 用于高频滤波器的跨导差分级，具有通用源的MOS差分输入对。 每个MOS输入的漏极连接到npn双极的发射极。 这两个匹配的双极子的栅极与第二极二极管连接的第三极的栅极连接在一起。 两个匹配的电流源馈送两个双极，第三个电流源馈送第三个双极。 单个受控电流吸收器连接到两个MOS输入晶体管的源极，并且（通过电阻器）连接到第三极。
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6.发明授权
公开(公告)号：US5200653A
公开(公告)日：1993-04-06
申请号：US718669
申请日：1991-06-21
申请人： David Moloney , Gianfranco Vai , Maurizio Zuffada , Giorgio Betti
发明人： David Moloney , Gianfranco Vai , Maurizio Zuffada , Giorgio Betti
IPC分类号： H03K19/0175 , H03K19/094 , H03K19/0948
CPC分类号： H03K19/0948 , H03K19/09429
摘要： The tristate output gate structure particularly for CMOS integrated circuits, comprises an enable terminal receiving an enable signal and an input terminal receiving an input signal, which connects, through signal switching means, an output terminal to a positive power supply terminal or to a negative power supply terminal. The enable terminal can be electrically connected to the gate terminal of a first P-channel transistor through signal inverting means and to the gate terminal of a second N-channel transistor. The output terminal is electrically connected to the drain terminals of the first and second transistors. The first and second transistors electrically insulate the output terminal from the input terminal.
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7.发明授权Apparatus for detecting undefined states of a finite state machine (FSM) and resetting the FSM upon detection 失效用于检测有限状态机（FSM）的未定义状态并在检测时复位FSM的装置
公开(公告)号：US5526486A
公开(公告)日：1996-06-11
申请号：US42856
申请日：1993-04-05
CPC分类号： G06F11/0763 , G06F11/085 , G06F11/28 , G06F7/00
摘要： A finite-state machine has combinatorial logic connected to a status memory which receives future state signals from the finite-state machine and sends current state signals to the finite-state machine. The combinatorial logic also receives and generates input and output signals which are external to the finite-state machine. The finite-state machine compares the future state signals to at least one reference level to set an error message to reset the finite-state machine for reliable computing and adjustment.
摘要翻译： 有限状态机具有连接到状态存储器的组合逻辑，其接收来自有限状态机的未来状态信号，并将当前状态信号发送到有限状态机。 组合逻辑还接收并产生在有限状态机外部的输入和输出信号。 有限状态机将未来状态信号与至少一个参考电平进行比较，以设置错误消息来重置有限状态机以进行可靠的计算和调整。
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公开(公告)号：US5394112A
公开(公告)日：1995-02-28
申请号：US35329
申请日：1993-03-22
申请人： Roberto Alini , Francesco Rezzi , Gianfranco Vai , Marco Gregori
发明人： Roberto Alini , Francesco Rezzi , Gianfranco Vai , Marco Gregori
CPC分类号： H03H11/0422 , H03F1/302 , H03F3/45089 , H03F3/45484 , H03H11/54 , H03F2203/45418 , H03F2203/45564 , H03F2203/45594 , H03F2203/45622 , H03F2203/45626 , H03F2203/45628 , H03F2203/45674 , H03F2203/45702
摘要： An integrated circuit transconductor stage which suppresses the dependence on temperature and production process variables of a differential transconductor stage. A negative feedback relation is used, where the output of the transconductor stage is connected to an additional current generator (which is referenced to a precision external resistor), to a capacitor, and also to the gate of a PMOS transistor which sources current to a polarization stage, which in turn sources current to the transconductor stage, or to multiple transconductor stages.
摘要翻译： 一种集成电路跨导级，其抑制了对差分跨导级的温度和生产工艺变量的依赖。 使用负反馈关系，其中跨导级的输出连接到附加电流发生器（以精密外部电阻器为基准），连接到电容器，以及连接到PMOS晶体管的栅极，PMOS晶体管将电流源源于 偏振级，其反过来将电流输送到跨导级，或者到多个跨导级。
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公开(公告)号：US5365193A
公开(公告)日：1994-11-15
申请号：US982376
申请日：1992-11-25
CPC分类号： H03F3/4508 , H03F1/223 , H03F3/45286 , H03F2203/45304 , H03F2203/45674 , H03F2203/45696
摘要： A circuit device for neutralizing thermal drift in a transconductor differential stage using a first circuit portion which corresponds structurally to the transconductor differential stage and has a pair of MOS input transistors defining a transconductance value which is substantially proportional to that of the transconductor differential stage, a pair of bipolar output transistors coupled to the MOS input transistors in a cascode configuration, and a second circuit portion being supplied a current from an output of the first differential portion to thereby output a current to be passed to the transconductor differential stage. The value of the output current is inversely proportional to temperature-dependent parameters of the transconductance.
摘要翻译： 一种电路装置，用于使用在结构上对应于跨导差分级的第一电路部分中和跨导差分级中的热漂移，并且具有一对限定跨导值的MOS输入晶体管，所述跨导值基本上与跨导差动级的导数值成正比， 一对双极性输出晶体管，其以共源共栅配置耦合到MOS输入晶体管;以及第二电路部分，从第一差分部分的输出端提供电流，从而输出要传递到跨导差分级的电流。 输出电流的值与跨导的温度相关参数成反比。
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公开(公告)号：US5912582A
公开(公告)日：1999-06-15
申请号：US866889
申请日：1997-05-30
CPC分类号： H03F3/72 , H03F3/45286 , H03F2203/45302 , H03F2203/45304 , H03F2203/45371 , H03F2203/45396 , H03F2203/45506
摘要： A BiCMOS transconductor differential stage for high frequency filters includes an input circuit portion having signal inputs and a pair of MOS transistors having their respective gate terminals corresponding to the signal inputs. The differential stage has an output circuit portion having signal outputs and a pair of bipolar transistors connected together with a common base inserted between the inputs and the outputs in a cascode configuration. The differential stage includes a switching device associated with at least one of the bipolar transistors to change the connections between parasitic capacitors present in the differential stage. The switching device also has at least one added bipolar transistor connected in a removable manner in parallel with the corresponding bipolar cascode transistor. In a variant differential stage, there are also provided respective added MOS transistors connected in parallel with the MOS transistors of the input circuit portion to change the ratio W:L of each of the MOS transistors.
摘要翻译： 用于高频滤波器的BiCMOS跨导差分级包括具有信号输入的输入电路部分和具有对应于信号输入的各自的栅极端子的一对MOS晶体管。 差分级具有具有信号输出的输出电路部分和一对双极晶体管，它们以共模基极连接在共模基底上，该公共基极以共源共栅配置插入在输入端和输出端之间。 差分级包括与双极晶体管中的至少一个相关联的开关器件，以改变差分级中存在的寄生电容器之间的连接。 开关器件还具有至少一个加法双极晶体管，其以可移除的方式与相应的双极共源共栅晶体管并联连接。 在变异差分级中，还提供了与输入电路部分的MOS晶体管并联连接的各个附加的MOS晶体管，以改变每个MOS晶体管的比率W：L。
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