公开(公告)号：US09540233B2

公开(公告)日：2017-01-10

申请号：US14194564

申请日：2014-02-28

Applicant: Microfabrica Inc.

Inventor： Ananda H. Kumar ,  Jorge S. Albarran ,  Adam L. Cohen ,  Kieun Kim ,  Michael S. Lockard ,  Uri Frodis ,  Dennis R. Smalley

IPC: B81C1/00 ,  C25D5/02

CPC classification number: B81C1/00666 ,  C25D5/022

Abstract: Electrochemical fabrication processes and apparatus for producing single layer or multi-layer structures where each layer includes the deposition of at least two materials and wherein the formation of at least some layers includes operations for reducing stress and/or curvature distortion when the structure is released from a sacrificial material which surrounded it during formation and possibly when released from a substrate on which it was formed. Six primary groups of embodiments are presented which are divide into eleven primary embodiments. Some embodiments attempt to remove stress to minimize distortion while others attempt to balance stress to minimize distortion.

Abstract translation: 用于生产单层或多层结构的电化学制造方法和装置，其中每个层包括至少两种材料的沉积，并且其中形成至少一些层包括当结构被释放时减少应力和/或曲率失真的操作 牺牲材料，其在形成期间包围它，并且可能当从其形成的基底释放时。 呈现了六个主要实施例的组，它们分为十一个主要实施例。 一些实施例尝试去除应力以最小化失真，而另一些实施例试图平衡应力以最小化失真。

公开(公告)号：US20140216941A1

公开(公告)日：2014-08-07

申请号：US14185530

申请日：2014-02-20

Applicant: Microfabrica Inc.

Inventor： Gang Zhang ,  Adam L. Cohen ,  Michael S. Lockard ,  Ananda H. Kumar ,  Ezekiel J.J. Kruglick ,  Kieun Kim

IPC: C25D5/50 ,  C25D5/02

CPC classification number: C25D5/50 ,  C25D1/003 ,  C25D5/022 ,  C25D5/10 ,  C25D5/12 ,  C25D5/14 ,  C25D5/18 ,  C25D5/34 ,  C25D5/40 ,  C25D5/48 ,  H01L21/2885 ,  H01L21/76879 ,  H05K3/241 ,  H05K3/243

Abstract: Multi-layer microscale or mesoscale structures are fabricated with adhered layers (e.g. layers that are bonded together upon deposition of successive layers to previous layers) and are then subjected to a heat treatment operation that enhances the interlayer adhesion significantly. The heat treatment operation is believed to result in diffusion of material across the layer boundaries and associated enhancement in adhesion (i.e. diffusion bonding). Interlayer adhesion and maybe intra-layer cohesion may be enhanced by heat treating in the presence of a reducing atmosphere that may help remove weaker oxides from surfaces or even from internal portions of layers.

Abstract translation: 多层微尺度或中尺度结构用粘附层（例如在连续层沉积到先前层上时结合在一起的层）制造，然后进行显着增强层间粘合的热处理操作。 认为热处理操作导致材料在层边界上的扩散，并且附着力增强（即扩散粘合）。 可以通过在有助于从表面甚至从内部部分去除较弱的氧化物的还原气氛的热处理来增强层间粘附和可能的层内内聚力。

公开(公告)号：US20140134453A1

公开(公告)日：2014-05-15

申请号：US14017535

申请日：2013-09-04

Applicant: Microfabrica Inc.

Inventor： Ming Ting Wu ,  Rulon J. Larsen, III ,  Young Kim ,  Kieun Kim ,  Adam L. Cohen ,  Ananda H. Kumar ,  Michael S. Lockard ,  Dennis R. Smalley

IPC: B32B15/01

CPC classification number: G01R1/06761 ,  B32B15/01 ,  Y10T428/12486

Abstract: Some embodiments of the invention are directed to electrochemical fabrication methods for forming structures or devices (e.g. microprobes for use in die level testing of semiconductor devices) from a core material and a shell or coating material that (1) partially coats the surface of the structure, (2) completely coats the surface of the structure, and/or (3) completely coats the surface of structural material of each layer from which the structure is formed including interlayer regions. These embodiments incorporate both the core material and the shell material into the structure as each layer is formed along with a sacrificial material that is removed after formation of all layers of the structure. In some embodiments the core material may be a material that would be removed with sacrificial material if it were accessible by an etchant during removal of the sacrificial material.

Abstract translation: 本发明的一些实施方案涉及用于从核心材料和壳或涂层材料形成结构或器件（例如用于半导体器件的晶片级测试的微探针）的电化学制造方法，（1）部分地涂覆结构的表面 ，（2）完全涂覆结构的表面，和/或（3）完全涂覆包含中间层区域的结构形成的各层结构材料的表面。 这些实施例将芯材料和壳体材料结合到结构中，因为每个层与形成所述结构的所有层之后被去除的牺牲材料一起形成。 在一些实施例中，芯材料可以是如果在去除牺牲材料期间可通过蚀刻剂使用牺牲材料将其去除的材料。

公开(公告)号：US20140008235A1

公开(公告)日：2014-01-09

申请号：US13657375

申请日：2012-10-22

Applicant: Microfabrica Inc.

Inventor： Dennis R. Smalley ,  Adam L. Cohen ,  Ananda H. Kumar ,  Michael S. Lockard

IPC: C25D5/02

CPC classification number: A61N1/00 ,  C23C18/1605 ,  C23C18/1651 ,  C25D1/003 ,  C25D1/20 ,  C25D5/022 ,  G01R1/0483 ,  G01R1/06716 ,  G01R1/07357 ,  G01R31/2886 ,  H05K3/467 ,  H05K3/4682

Abstract: Electrochemical fabrication processes and apparatus for producing multi-layer structures where each layer includes the deposition of at least two materials and wherein the formation of at least some layers including operations for providing coatings of dielectric material that isolate at least portions of a first conductive material from (1) other portions of the first conductive material, (2) a second conductive material, or (3) another dielectric material, and wherein the thickness of the dielectric coatings are thin compared to the thicknesses of the layers used in forming the structures. In some preferred embodiments, portions of each individual layer are encapsulated by dielectric material while in other embodiments only boundaries between distinct regions of materials are isolated from one another by dielectric barriers.

Abstract translation: 用于生产多层结构的电化学制造方法和装置，其中每个层包括至少两种材料的沉积，并且其中形成至少一些层，包括用于提供将第一导电材料的至少一部分与 （1）第一导电材料的其它部分，（2）第二导电材料或（3）另一种电介质材料，并且其中电介质涂层的厚度与用于形成结构的层的厚度相比较薄。 在一些优选实施例中，每个单独层的部分被电介质材料包封，而在其它实施例中，材料的不同区域之间的边界通过电介质屏障彼此隔离。

公开(公告)号：US20160258075A1

公开(公告)日：2016-09-08

申请号：US15091537

申请日：2016-04-05

Applicant: Microfabrica Inc.

Inventor： Dennis R. Smalley ,  Adam L. Cohen ,  Ananda H. Kumar ,  Michael S. Lockard

IPC: C25D1/00 ,  H05K3/46 ,  C25D1/20

CPC classification number: A61N1/00 ,  C23C18/1605 ,  C23C18/1651 ,  C25D1/003 ,  C25D1/20 ,  C25D5/022 ,  G01R1/0483 ,  G01R1/06716 ,  G01R1/07357 ,  G01R31/2886 ,  H05K3/467 ,  H05K3/4682

Abstract: Electrochemical fabrication processes and apparatus for producing multi-layer structures where each layer includes the deposition of at least two materials and wherein the formation of at least some layers including operations for providing coatings of dielectric material that isolate at least portions of a first conductive material from (1) other portions of the first conductive material, (2) a second conductive material, or (3) another dielectric material, and wherein the thickness of the dielectric coatings are thin compared to the thicknesses of the layers used in forming the structures. In some preferred embodiments, portions of each individual layer are encapsulated by dielectric material while in other embodiments only boundaries between distinct regions of materials are isolated from one another by dielectric barriers.

Abstract translation: 用于生产多层结构的电化学制造方法和装置，其中每个层包括至少两种材料的沉积，并且其中形成至少一些层，包括用于提供将第一导电材料的至少一部分与 （1）第一导电材料的其它部分，（2）第二导电材料或（3）另一种电介质材料，并且其中电介质涂层的厚度与用于形成结构的层的厚度相比较薄。 在一些优选实施例中，每个单独层的部分被电介质材料包封，而在其它实施例中，材料的不同区域之间的边界通过电介质屏障彼此隔离。

公开(公告)号：US20150108002A1

公开(公告)日：2015-04-23

申请号：US14572472

申请日：2014-12-16

Applicant: Microfabrica Inc.

Inventor： Kieun Kim ,  Adam L. Cohen ,  Willa M. Larsen ,  Richard Chen ,  Ananda H. Kumar ,  Ezekiel J.J. Kruglick ,  Vacit Arat ,  Gang Zhang ,  Michael S. Lockard ,  Christopher A. Bang ,  Jeffrey A. Thompson

IPC: C25D5/02 ,  C25D7/00

CPC classification number: C25D1/003

Abstract: Embodiments of the present invention are directed to the formation of microprobe tips elements having a variety of configurations. In some embodiments tips are formed from the same building material as the probes themselves, while in other embodiments the tips may be formed from a different material and/or may include a coating material. In some embodiments, the tips are formed before the main portions of the probes and the tips are formed in proximity to or in contact with a temporary substrate. Probe tip patterning may occur in a variety of different ways, including, for example, via molding in patterned holes that have been isotropically or anisotropically etched silicon, via molding in voids formed in exposed photoresist, via molding in voids in a sacrificial material that have formed as a result of the sacrificial material mushrooming over carefully sized and located regions of dielectric material, via isotropic etching of the tip material around carefully sized and placed etching shields, via hot pressing, and the like.

Abstract translation: 本发明的实施例涉及形成具有各种构造的微探针尖元件。 在一些实施例中，尖端由与探针本身相同的建筑材料形成，而在其它实施例中，尖端可以由不同的材料形成和/或可以包括涂层材料。 在一些实施例中，尖端在探针的主要部分之前形成，并且尖端形成在临时衬底附近或与临时衬底接触。 探针尖端图案化可以以各种不同的方式发生，包括例如通过在各向异性或各向异性地蚀刻硅的图案化孔中模制，通过在曝光的光致抗蚀剂中形成的空隙中模制，通过在牺牲材料中的空隙中模制， 由于牺牲材料通过电介质材料的细小尺寸和定位的区域，经由热压等等仔细地尺寸和放置的蚀刻屏蔽部分上的尖端材料的各向同性蚀刻而形成。

公开(公告)号：US20140238865A1

公开(公告)日：2014-08-28

申请号：US14194564

申请日：2014-02-28

Applicant: Microfabrica Inc.

Inventor： Ananda H. Kumar ,  Jorge S. Alberron ,  Adam L. Cohen ,  Kieun Kim ,  Michael S. Lockard ,  Uri Frodis ,  Dennis R. Smalley

IPC: B81C1/00 ,  C25D5/02

CPC classification number: B81C1/00666 ,  C25D5/022

Abstract: Electrochemical fabrication processes and apparatus for producing single layer or multi-layer structures where each layer includes the deposition of at least two materials and wherein the formation of at least some layers includes operations for reducing stress and/or curvature distortion when the structure is released from a sacrificial material which surrounded it during formation and possibly when released from a substrate on which it was formed. Six primary groups of embodiments are presented which are divide into eleven primary embodiments. Some embodiments attempt to remove stress to minimize distortion while others attempt to balance stress to minimize distortion.

Abstract translation: 用于生产单层或多层结构的电化学制造方法和装置，其中每个层包括至少两种材料的沉积，并且其中形成至少一些层包括当结构被释放时减少应力和/或曲率失真的操作 牺牲材料，其在形成期间包围它，并且可能当从其形成的基底释放时。 呈现了六个主要实施例的组，它们分为十一个主要实施例。 一些实施例尝试去除应力以最小化失真，而另一些实施例试图平衡应力以最小化失真。