公开(公告)号：US20230386575A1

公开(公告)日：2023-11-30

申请号：US17752207

申请日：2022-05-24

Applicant: Micron Technology, Inc.

Inventor： Haoyu Li ,  John D. Hopkins ,  Collin Howder ,  Adam W. Saxler

IPC: G11C16/04 ,  H01L27/11519 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/11582

CPC classification number: G11C16/0483 ,  H01L27/11519 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/11582

Abstract: A memory array comprising strings of memory cells comprises a conductor tier comprising conductor material. Laterally-spaced memory blocks individually comprise a vertical stack comprising alternating insulative tiers and conductive tiers. Channel-material strings of memory cells extend through the insulative tiers and the conductive tiers. Conducting material of a lower of the conductive tiers directly electrically coupling together the channel material of individual of the channel-material strings and the conductor material of the conductor tier. The conducting material in the lower conductive tier comprises upper conductively-doped semiconductive material, lower conductively-doped semiconductive material, and intermediate material vertically there-between. The intermediate material is of different composition from those of the upper conductively-doped semiconductive material and the lower conductively-doped semiconductive material and comprises at least one of carbon, nitrogen, oxygen, metal, and n-type doped material also comprising boron. Other embodiments, including method, re disclosed.

公开(公告)号：US20230057754A1

公开(公告)日：2023-02-23

申请号：US17407449

申请日：2021-08-20

Applicant: Micron Technology, Inc.

Inventor： Adam W. Saxler

IPC: H01L23/528 ,  H01L23/522 ,  H01L23/532 ,  H01L21/768 ,  H01L27/11519 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/11582 ,  H01L27/1157 ,  H01L27/11565

Abstract: A microelectronic device comprises a stack structure, and slot structures vertically extending through the stack structure and dividing the stack structure into block structures. Each of the slot structures individually comprises an insulative liner material vertically extending though the slot structure and contacting sidewalls of the insulative levels and the conductive levels defining the slot structure, and grains of a material in contact with sidewalls of the insulative liner material. The grains of the material comprise first grains spanning an entire width between the sidewalls of the insulative liner material. Related memory devices, electronic systems, and methods are also described.

公开(公告)号：US20210050364A1

公开(公告)日：2021-02-18

申请号：US16542645

申请日：2019-08-16

Applicant: Micron Technology, Inc.

Inventor： Nicholas R. Tapias ,  Andrew Li ,  Adam W. Saxler ,  Kunal Shrotri ,  Erik R. Byers ,  Matthew J. King ,  Diem Thy N. Tran ,  Wei Yeeng Ng ,  Anish A. Khandekar

IPC: H01L27/11582 ,  H01L27/11556 ,  H01L21/02 ,  H01L21/285

Abstract: Some embodiments include a structure having an opening extending into an integrated configuration. A first material is within the opening, and is configured to create an undulating topography relative to a sidewall of the opening. The undulating topography has a surface roughness characterized by a mean roughness parameter Rmean which is the mean peak-to-valley distance along the undulating topography. The Rmean is at least about 4 nm. A second material is within the opening and along at least a portion of the undulating topography. The first and second materials are compositionally different from one another. Some embodiments include integrated assemblies. Some embodiments include methods of forming integrated assemblies.

公开(公告)号：US20240321745A1

公开(公告)日：2024-09-26

申请号：US18677693

申请日：2024-05-29

Applicant: Micron Technology, Inc.

Inventor： Adam W. Saxler

IPC: H01L23/528 ,  H01L21/768 ,  H01L23/522 ,  H01L23/532 ,  H10B41/10 ,  H10B41/27 ,  H10B41/35 ,  H10B43/10 ,  H10B43/27 ,  H10B43/35

CPC classification number: H01L23/5283 ,  H01L21/76831 ,  H01L21/76877 ,  H01L23/5226 ,  H01L23/53266 ,  H10B41/10 ,  H10B41/27 ,  H10B41/35 ,  H10B43/10 ,  H10B43/27 ,  H10B43/35

Abstract: A microelectronic device comprises a stack structure, and slot structures vertically extending through the stack structure and dividing the stack structure into block structures. Each of the slot structures individually comprises an insulative liner material vertically extending through the slot structure and contacting sidewalls of the insulative levels and the conductive levels defining the slot structure, and grains of a material in contact with sidewalls of the insulative liner material. The grains of the material comprise first grains spanning an entire width between the sidewalls of the insulative liner material. Related memory devices, electronic systems, and methods are also described.

公开(公告)号：US11758716B2

公开(公告)日：2023-09-12

申请号：US16555033

申请日：2019-08-29

Applicant: Micron Technology, Inc.

Inventor： Adam W. Saxler

IPC: H01L27/06 ,  H10B41/27 ,  H10B41/35

CPC classification number: H10B41/27 ,  H01L27/0605 ,  H10B41/35

Abstract: An electronic device comprises an array of memory cells comprising a channel material laterally proximate to tiers of alternating conductive materials and dielectric materials. The channel material comprises a heterogeneous semiconductive material varying in composition across a width thereof. Related electronic systems and methods are also disclosed.

公开(公告)号：US20210126193A1

公开(公告)日：2021-04-29

申请号：US16665679

申请日：2019-10-28

Applicant: Micron Technology, Inc.

Inventor： Santanu Sarkar ,  Robert K. Grubbs ,  Farrell M. Good ,  Adam W. Saxler ,  Andrea Gotti

IPC: H01L45/00

Abstract: An electronic device comprising a stack structure comprising one or more stacks of materials and a metal oxide material adjacent to the stacks of materials. The materials of the stacks comprise one or more chalcogenide materials. The metal oxide material comprises aluminum oxide, aluminum silicate, hafnium oxide, hafnium silicate, zirconium oxide, zirconium silicate, or a combination thereof and the metal oxide material extends continuously from an upper portion of the one or more stacks of materials to a lower portion of the one or more stacks of materials. Additional electronic devices are disclosed, as are related systems and methods of forming an electronic device.

公开(公告)号：US12027460B2

公开(公告)日：2024-07-02

申请号：US17407449

申请日：2021-08-20

Applicant: Micron Technology, Inc.

Inventor： Adam W. Saxler

IPC: H01L23/528 ,  H01L21/768 ,  H01L23/522 ,  H01L23/532 ,  H10B41/10 ,  H10B41/27 ,  H10B41/35 ,  H10B43/10 ,  H10B43/27 ,  H10B43/35

CPC classification number: H01L23/5283 ,  H01L21/76831 ,  H01L21/76877 ,  H01L23/5226 ,  H01L23/53266 ,  H10B41/10 ,  H10B41/27 ,  H10B41/35 ,  H10B43/10 ,  H10B43/27 ,  H10B43/35

Abstract: A microelectronic device comprises a stack structure, and slot structures vertically extending through the stack structure and dividing the stack structure into block structures. Each of the slot structures individually comprises an insulative liner material vertically extending through the slot structure and contacting sidewalls of the insulative levels and the conductive levels defining the slot structure, and grains of a material in contact with sidewalls of the insulative liner material. The grains of the material comprise first grains spanning an entire width between the sidewalls of the insulative liner material. Related memory devices, electronic systems, and methods are also described.

公开(公告)号：US20220376176A1

公开(公告)日：2022-11-24

申请号：US17818313

申请日：2022-08-08

Applicant: Micron Technology, Inc.

Inventor： Santanu Sarkar ,  Robert K. Grubbs ,  Farrell M. Good ,  Adam W. Saxler ,  Andrea Gotti

IPC: H01L45/00 ,  H01L27/24

Abstract: An electronic device comprising a stack structure comprising one or more stacks of materials and a metal oxide material adjacent to the stacks of materials. The materials of the stacks comprise one or more chalcogenide materials. The metal oxide material comprises aluminum oxide, aluminum silicate, hafnium oxide, hafnium silicate, zirconium oxide, zirconium silicate, or a combination thereof and the metal oxide material extends continuously from an upper portion of the one or more stacks of materials to a lower portion of the one or more stacks of materials. Additional electronic devices are disclosed, as are related systems and methods of forming an electronic device.

公开(公告)号：US11444243B2

公开(公告)日：2022-09-13

申请号：US16665679

申请日：2019-10-28

Applicant: Micron Technology, Inc.

Inventor： Santanu Sarkar ,  Robert K. Grubbs ,  Farrell M. Good ,  Adam W. Saxler ,  Andrea Gotti

IPC: H01L45/00

Abstract: An electronic device comprising a stack structure comprising one or more stacks of materials and a metal oxide material adjacent to the stacks of materials. The materials of the stacks comprise one or more chalcogenide materials. The metal oxide material comprises aluminum oxide, aluminum silicate, hafnium oxide, hafnium silicate, zirconium oxide, zirconium silicate, or a combination thereof and the metal oxide material extends continuously from an upper portion of the one or more stacks of materials to a lower portion of the one or more stacks of materials. Additional electronic devices are disclosed, as are related systems and methods of forming an electronic device.

公开(公告)号：US20240098993A1

公开(公告)日：2024-03-21

申请号：US17948521

申请日：2022-09-20

Applicant: Micron Technology, Inc.

Inventor： Andrew Li ,  Sidhartha Gupta ,  Adam W. Saxler

IPC: H01L27/11582 ,  H01L27/11556

CPC classification number: H01L27/11582 ,  H01L27/11556

Abstract: A memory array comprising strings of memory cells comprises laterally-spaced memory blocks individually comprising a vertical stack comprising alternating insulative tiers and conductive tiers above a conductor tier. Strings of memory cells comprise channel-material strings that extend through the insulative tiers and the conductive tiers in the memory blocks. The channel-material strings directly electrically couple to conductor material of the conductor tier. Intervening material is laterally-between and longitudinally-along immediately-laterally-adjacent of the memory blocks. The intervening material comprises a laterally-outer insulative lining extending longitudinally-along the immediately-laterally-adjacent memory-blocks. The laterally-outer insulative lining has its lowest surface between a top and a bottom of the lowest conductive tier. The laterally-outer insulative lining has its highest surface at or below a lowest surface of the next-lowest conductive tier. Laterally-inner insulating material extends longitudinally-along the immediately-laterally-adjacent memory blocks laterally-inward of the laterally-outer insulative lining. An interface is between the laterally-outer insulative lining and the laterally-inner insulating material. Methods are also disclosed.