公开(公告)号：US20250094047A1

公开(公告)日：2025-03-20

申请号：US18782539

申请日：2024-07-24

Applicant: Micron Technology, Inc.

Inventor： Marco Sforzin ,  Rishabh Dubey ,  Daniele Balluchi ,  Danilo Caraccio ,  Emanuele Confalonieri ,  Nicola Del Gatto

IPC: G06F3/06

Abstract: A variety of applications can include a memory device implementing a dual compression scheme. A memory subsystem of the memory device can be arranged into multiple regions. A first region of the memory subsystem can be used to store non-compressible data. A second region can be used to store compressible data. The second region can have a first subregion and a second subregion. The first subregion can be used to accept compressible data as non-compressed data corresponding to a compression ratio being less than a threshold compression ratio. The second subregion can be used to accept compressed data corresponding to a compression ratio being greater than the threshold compression ratio. Additional apparatus, systems, and methods are disclosed.

公开(公告)号：US20250053343A1

公开(公告)日：2025-02-13

申请号：US18929332

申请日：2024-10-28

Applicant: Micron Technology, Inc.

Inventor： Amitava Majumdar ,  Anandhavel Nagendrakumar ,  Mohammed Ebrahim Hargan ,  Scott Garner ,  Danilo Caraccio ,  Daniele Balluchi ,  Chia Wei Chang ,  Ankush Lal

IPC: G06F3/06 ,  G11C11/406

Abstract: An apparatus can include a number of memory devices and a memory controller coupled to one or more of the number of memory devices. The memory controller can include a row hammer detector. The memory controller can be configured increment for a first time period a row counter in a first data structure and a refresh counter. The memory controller can be configured to increment for a second time period a row counter in a second data structure and the refresh counter. The memory controller can be configured to determine that a value of the refresh counter exceeds a refresh threshold and responsive to the determination that the value of the refresh counter exceeds the refresh threshold, issue a notification.

公开(公告)号：US12154655B2

公开(公告)日：2024-11-26

申请号：US17861231

申请日：2022-07-10

Applicant: Micron Technology, Inc.

Inventor： Daniele Balluchi ,  Marco Sforzin

IPC: G11C11/22 ,  G06F11/07 ,  G11C7/10 ,  G11C7/12

Abstract: Systems, apparatuses, and methods related to a flip-on-precharge disable operation are described herein. In an example, a method can include receiving a command to perform a precharge operation on a set of memory cells in a memory device. The memory device can include a plurality of sets of memory cells corresponding to respective portions of an array of memory cells of the memory device. The method can further include accessing one or more sets of bits in a mode register. The one or more sets of bits in the mode register indicate address locations of the plurality of sets of memory cells to disable the flip on precharge operation. The method can further include performing the precharge operation on the set of memory cells. The flip on precharge operation associated with the precharge operation can be disabled for those sets of the plurality of sets of memory cells whose address locations are in the mode register.

公开(公告)号：US12131071B2

公开(公告)日：2024-10-29

申请号：US18121874

申请日：2023-03-15

Applicant: Micron Technology, Inc.

Inventor： Amitava Majumdar ,  Anandhavel Nagendrakumar ,  Mohammed Ebrahim Hargan ,  Scott Garner ,  Danilo Caraccio ,  Daniele Balluchi ,  Chia Wei Chang ,  Ankush Lal

IPC: G06F3/06 ,  G11C11/406

CPC classification number: G06F3/0659 ,  G06F3/0619 ,  G06F3/0673 ,  G11C11/406

Abstract: An apparatus can include a number of memory devices and a memory controller coupled to one or more of the number of memory devices. The memory controller can include a row hammer detector. The memory controller can be configured increment for a first time period a row counter in a first data structure and a refresh counter. The memory controller can be configured to increment for a second time period a row counter in a second data structure and the refresh counter. The memory controller can be configured to determine that a value of the refresh counter exceeds a refresh threshold and responsive to the determination that the value of the refresh counter exceeds the refresh threshold, issue a notification.

公开(公告)号：US20240094991A1

公开(公告)日：2024-03-21

申请号：US17945260

申请日：2022-09-15

Applicant: Micron Technology, Inc.

Inventor： Marco Sforzin ,  Daniele Balluchi

IPC: G06F7/58 ,  G11C11/4076 ,  H03K3/84 ,  H03K19/21

CPC classification number: G06F7/582 ,  G11C11/4076 ,  H03K3/84 ,  H03K19/21

Abstract: Methods, systems, and devices related to generating, by a pseudorandom binary sequence (PRBS) generator of a memory module, a PRBS comprising a first plurality of bits corresponding to a plurality of cycles of a clock signal of the memory module subsequent to a current cycle of the clock signal. Generation of the PRBS can be based on an intermediate PRBS comprising a second plurality of bits corresponding to the current cycle of the clock signal. During each respective cycle of the clock signal, a respective subset of the PRBS can be communicated from the PRBS generator to a memory device of the memory module. Each respective subset of the PRBS comprises a quantity of bits based on a frequency of a data strobe signal of the memory device relative to a frequency of the clock signal.

公开(公告)号：US20240087664A1

公开(公告)日：2024-03-14

申请号：US17943706

申请日：2022-09-13

Applicant: Micron Technology, Inc.

Inventor： William Yu ,  Daniele Balluchi ,  Chad B. Erickson ,  Danilo Caraccio

IPC: G11C29/38 ,  G11C29/10 ,  G11C29/12

CPC classification number: G11C29/38 ,  G11C29/10 ,  G11C29/1201

Abstract: Methods, systems, and devices related to built-in self-test burst patterns based on architecture of memory. A controller can be coupled to a memory device. The controller can include built-in self-test (BIST) circuitry. The BIST circuitry can include registers configured to store respective write burst patterns and read burst patterns based on an architecture of the memory device.

公开(公告)号：US20240061792A1

公开(公告)日：2024-02-22

申请号：US18235289

申请日：2023-08-17

Applicant: Micron Technology, Inc.

Inventor： Emanuele Confalonieri ,  Paolo Amato ,  Daniele Balluchi ,  Marco Sforzin ,  Danilo Caraccio ,  Niccolò Izzo ,  Graziano Mirichigni ,  Massimiliano Patriarca

IPC: G06F12/14 ,  G06F12/0804

CPC classification number: G06F12/1458 ,  G06F12/0804

Abstract: Systems, apparatuses, and methods related to data identity recognition for semiconductor devices are described. A system includes a host and a memory device coupled to the host via an interconnect bus. The host includes a host security manager configured to encrypt data of a command, perform a memory integrity check, allow access to memory of a memory device corresponding to an address of a command based on which entity associated with the host sent the command, generate security keys, program security keys into the memory device, program encryption ranges, or any combination thereof. The memory device includes a memory encryption manager and a memory device security manager. The memory device security manager is configured to detect whether a command was sent from a trusted domain of the host or non-trusted domain of the host and identify which entity associated with the host initiated the command.

公开(公告)号：US11880276B2

公开(公告)日：2024-01-23

申请号：US18099800

申请日：2023-01-20

Applicant: Micron Technology, Inc.

Inventor： Danilo Caraccio ,  Daniele Balluchi

IPC: G11C29/00 ,  G06F11/10 ,  G06F11/07 ,  G06F11/30 ,  G06F12/02

CPC classification number: G06F11/1068 ,  G06F11/076 ,  G06F11/0772 ,  G06F11/3037 ,  G06F12/0238 ,  G06F2212/7201

Abstract: Methods, systems, and devices for maintenance command interfaces for a memory system are described. A host system and a memory system may be configured according to a shared protocol that supports enhanced management of maintenance operations between the host system and memory system, such as maintenance operations to resolve error conditions at a physical address of a memory system. In some examples, a memory system may initiate maintenance operations based on detections performed at the memory system, and the memory system may provide a maintenance indication for the host system. In some examples, a host system may initiate maintenance operations based on detections performed at the host system. In various examples, the described maintenance signaling may include capability signaling between the host system and memory system, status indications between the host system and memory system, and other maintenance management techniques.

公开(公告)号：US20240013822A1

公开(公告)日：2024-01-11

申请号：US17861231

申请日：2022-07-10

Applicant: Micron Technology, Inc.

Inventor： Daniele Balluchi ,  Marco Sforzin

IPC: G11C7/12 ,  G11C7/10 ,  G06F11/07

CPC classification number: G11C7/12 ,  G11C7/1069 ,  G06F11/0793 ,  G06F11/073

Abstract: Systems, apparatuses, and methods related to a flip-on-precharge disable operation are described herein. In an example, a method can include receiving a command to perform a precharge operation on a set of memory cells in a memory device. The memory device can include a plurality of sets of memory cells corresponding to respective portions of an array of memory cells of the memory device. The method can further include accessing one or more sets of bits in a mode register. The one or more sets of bits in the mode register indicate address locations of the plurality of sets of memory cells to disable the flip on precharge operation. The method can further include performing the precharge operation on the set of memory cells. The flip on precharge operation associated with the precharge operation can be disabled for those sets of the plurality of sets of memory cells whose address locations are in the mode register.

公开(公告)号：US20240004760A1

公开(公告)日：2024-01-04

申请号：US18216160

申请日：2023-06-29

Applicant: Micron Technology, Inc.

Inventor： Paolo Amato ,  Daniele Balluchi ,  Danilo Caraccio ,  Emanuele Confalonieri ,  Marco Sforzin

IPC: G06F11/10

CPC classification number: G06F11/1076

Abstract: A channel width can depend on a quantity of memory units (e.g., memory dice) that forms a channel as well as a size of the memory units. A memory system can operate with memory units configured to exchange (e.g., transfer to and/or from) data at a rate of smaller granularity that can provide more various options for channel widths, which can further allow a fine-tuned optimization of the memory system in association with its bandwidth and latency in transferring data from and/or to the memory units. The channels whose channel width is fine-tuned with such memory units can be further used to provide a reliability, availability, and serviceability (RAS) protection, such as a redundant array of independent disks (RAID) protection.