公开(公告)号：US11501804B2

公开(公告)日：2022-11-15

申请号：US16992589

申请日：2020-08-13

Applicant: Micron Technology, Inc.

Inventor： Fredrick D. Fishburn ,  Si-Woo Lee ,  Scott L. Light ,  Song Guo

IPC: H01L27/108 ,  G11C5/06

Abstract: A microelectronic device comprises a semiconductive pillar structure comprising a central portion, a first end portion, and a second end portion on a side of the central portion opposite the first end portion, the first end portion oriented at an angle with respect to the central portion and extending substantially parallel to the second end portion, a digit line contact on the central portion of the semiconductive pillar structure, a first storage node contact on the first end portion, and a second storage node contact on the second end portion. Related microelectronic devices, electronic systems, and methods are also described.

公开(公告)号：US11004494B2

公开(公告)日：2021-05-11

申请号：US16267087

申请日：2019-02-04

Applicant: Micron Technology, Inc.

Inventor： Sanh D. Tang ,  Kuo-Chen Wang ,  Martin C. Roberts ,  Diem Thy N. Tran ,  Hideki Gomi ,  Fredrick D. Fishburn ,  Srinivas Pulugurtha ,  Michel Koopmans ,  Eiji Hasunuma

IPC: G11C11/24 ,  G11C11/402 ,  H01L27/108 ,  G11C5/06 ,  G11C11/4097 ,  G11C5/02 ,  G11C8/14

Abstract: Some embodiments include an assembly having active material structures arranged in an array having rows and columns. Each of the active material structures has a first side which includes a bit contact region, and has a second side which includes a cell contact region. Each of the bit contact regions is coupled with a first redistribution pad. Each of the cell contact regions is coupled with a second redistribution pad. The first redistribution pads are coupled with bitlines, and the second redistribution pads are coupled with programmable devices. Some embodiments include methods of forming memory arrays.

公开(公告)号：US20200295007A1

公开(公告)日：2020-09-17

申请号：US16887338

申请日：2020-05-29

Applicant: Micron Technology, Inc.

Inventor： Fredrick D. Fishburn

IPC: H01L27/108

Abstract: Some embodiments include an assembly having a stack of first and second alternating levels. The first levels are insulative levels. The second levels are device levels having integrated devices. Each of the integrated devices has a transistor coupled with an associated capacitor, and the capacitor is horizontally offset from the transistor. The transistors have semiconductor channel material, and have transistor gates along the semiconductor channel material. Each of the transistors has a first source/drain region along one side of the semiconductor channel material and coupled with the associated capacitor, and has a second source/drain region. Wordlines extend horizontally along the device levels and are coupled with the transistor gates. Digit lines extend vertically through the device levels and are coupled with the second source/drain regions. Some embodiments include methods of forming integrated structures.

公开(公告)号：US11081487B2

公开(公告)日：2021-08-03

申请号：US16887338

申请日：2020-05-29

Applicant: Micron Technology, Inc.

Inventor： Fredrick D. Fishburn

IPC: H01L27/108

Abstract: Some embodiments include an assembly having a stack of first and second alternating levels. The first levels are insulative levels. The second levels are device levels having integrated devices. Each of the integrated devices has a transistor coupled with an associated capacitor, and the capacitor is horizontally offset from the transistor. The transistors have semiconductor channel material, and have transistor gates along the semiconductor channel material. Each of the transistors has a first source/drain region along one side of the semiconductor channel material and coupled with the associated capacitor, and has a second source/drain region. Wordlines extend horizontally along the device levels and are coupled with the transistor gates. Digit lines extend vertically through the device levels and are coupled with the second source/drain regions. Some embodiments include methods of forming integrated structures.

公开(公告)号：US20190172517A1

公开(公告)日：2019-06-06

申请号：US16267087

申请日：2019-02-04

Applicant: Micron Technology, Inc.

Inventor： Sanh D. Tang ,  Kuo-Chen Wang ,  Martin C. Roberts ,  Diem Thy N. Tran ,  Hideki Gomi ,  Fredrick D. Fishburn ,  Srinivas Pulugurtha ,  Michel Koopmans ,  Eiji Hasunuma

IPC: G11C11/402 ,  G11C5/06 ,  H01L27/108

Abstract: Some embodiments include an assembly having active material structures arranged in an array having rows and columns. Each of the active material structures has a first side which includes a bit contact region, and has a second side which includes a cell contact region. Each of the bit contact regions is coupled with a first redistribution pad. Each of the cell contact regions is coupled with a second redistribution pad. The first redistribution pads are coupled with bitlines, and the second redistribution pads are coupled with programmable devices. Some embodiments include methods of forming memory arrays.

公开(公告)号：US20210343719A1

公开(公告)日：2021-11-04

申请号：US17378043

申请日：2021-07-16

Applicant: Micron Technology, Inc.

Inventor： Fredrick D. Fishburn

IPC: H01L27/108

Abstract: Some embodiments include an assembly having a stack of first and second alternating levels. The first levels are insulative levels. The second levels are device levels having integrated devices. Each of the integrated devices has a transistor coupled with an associated capacitor, and the capacitor is horizontally offset from the transistor. The transistors have semiconductor channel material, and have transistor gates along the semiconductor channel material. Each of the transistors has a first source/drain region along one side of the semiconductor channel material and coupled with the associated capacitor, and has a second source/drain region. Wordlines extend horizontally along the device levels and are coupled with the transistor gates. Digit lines extend vertically through the device levels and are coupled with the second source/drain regions. Some embodiments include methods of forming integrated structures.

公开(公告)号：US20210050409A1

公开(公告)日：2021-02-18

申请号：US16543065

申请日：2019-08-16

Applicant: Micron Technology, Inc.

Inventor： Matthew N. Rocklein ,  An-Jen B. Cheng ,  Fredrick D. Fishburn ,  Sevim Korkmaz ,  Paul A. Paduano

IPC: H01L49/02 ,  H01L21/285 ,  H01L21/02 ,  H01L21/311

Abstract: Methods, apparatuses, and systems related to trim a semiconductor structure using oxygen are described. An example method includes forming a support structure for a semiconductor structure having a first silicate material on a working surface. The method further includes forming a first nitride material on the first silicate material. The method further includes forming a second silicate material on the first nitride material. The method further includes forming a second nitride material on the second silicate material. The method further includes forming an opening through the semiconductor structure. The method further includes depositing an electrode material within the opening. The method further includes removing portions of the support structure. The method further includes performing a controlled oxidative trim to an upper portion of the electrode material.

公开(公告)号：US10833087B2

公开(公告)日：2020-11-10

申请号：US16107324

申请日：2018-08-21

Applicant: Micron Technology, Inc.

Inventor： Fredrick D. Fishburn ,  Haitao Liu ,  Soichi Sugiura ,  Oscar O. Enomoto ,  Mark A. Zaleski ,  Keisuke Hirofuji ,  Makoto Morino ,  Ichiro Abe ,  Yoshiyuki Nanjo ,  Atsuko Otsuka

IPC: H01L27/00 ,  H01L27/108 ,  H01L29/423 ,  H01L29/66

Abstract: A semiconductor device comprises a memory storage component and a transistor in operable communication with the memory storage element. The transistor comprises a source region, a drain region, a gate electrode between the source region and the drain region, a charge trapping material surrounding at least an upper portion of the gate electrode, and an oxide material on sides of the charge trapping material. Related systems and methods are also disclosed.

公开(公告)号：US20200066726A1

公开(公告)日：2020-02-27

申请号：US16107324

申请日：2018-08-21

Applicant: Micron Technology, Inc.

Inventor： Fredrick D. Fishburn ,  Haitao Liu ,  Soichi Sugiura ,  Oscar O. Enomoto ,  Mark A. Zaleski ,  Keisuke Hirofuji ,  Makoto Morino ,  Ichiro Abe ,  Yoshiyuki Nanjo ,  Atsuko Otsuka

IPC: H01L27/108 ,  H01L29/423 ,  H01L29/66

Abstract: A semiconductor device comprises a memory storage component and a transistor in operable communication with the memory storage element. The transistor comprises a source region, a drain region, a gate electrode between the source region and the drain region, a charge trapping material surrounding at least an upper portion of the gate electrode, and an oxide material on sides of the charge trapping material. Related systems and methods are also disclosed.

公开(公告)号：US11626406B2

公开(公告)日：2023-04-11

申请号：US17378043

申请日：2021-07-16

Applicant: Micron Technology, Inc.

Inventor： Fredrick D. Fishburn

IPC: H01L27/108 ,  H01L25/065

Abstract: Some embodiments include an assembly having a stack of first and second alternating levels. The first levels are insulative levels. The second levels are device levels having integrated devices. Each of the integrated devices has a transistor coupled with an associated capacitor, and the capacitor is horizontally offset from the transistor. The transistors have semiconductor channel material, and have transistor gates along the semiconductor channel material. Each of the transistors has a first source/drain region along one side of the semiconductor channel material and coupled with the associated capacitor, and has a second source/drain region. Wordlines extend horizontally along the device levels and are coupled with the transistor gates. Digit lines extend vertically through the device levels and are coupled with the second source/drain regions. Some embodiments include methods of forming integrated structures.