公开(公告)号：US11990199B2

公开(公告)日：2024-05-21

申请号：US17647152

申请日：2022-01-05

Applicant: Micron Technology, Inc.

Inventor： Taeksang Song ,  Saira Samar Malik ,  Hyunyoo Lee ,  Chinnakrishnan Ballapuram ,  Kang-Yong Kim

IPC: G11C29/42 ,  G11C29/12 ,  G11C29/44

CPC classification number: G11C29/42 ,  G11C29/1201 ,  G11C29/4401

Abstract: Methods, systems, and devices for centralized error correction circuit are described. An apparatus may include a non-volatile memory disposed on a first die and a volatile memory disposed on a second die (different than the first die). The apparatus may also include an interface controller disposed on a third die (different than the first die and the second die). The interface controller may be coupled with the non-volatile memory and the volatile memory and may include an error correction circuit that is configured to operate on one or more codewords received from the volatile memory.

公开(公告)号：US11869626B2

公开(公告)日：2024-01-09

申请号：US17502792

申请日：2021-10-15

Applicant: Micron Technology, Inc.

Inventor： Kang-Yong Kim ,  Hyunyoo Lee

IPC: G11C7/10

CPC classification number: G11C7/1063 ,  G11C7/109 ,  G11C7/1066 ,  G11C7/1093

Abstract: Some memory dies in a stack can be connected externally to the stack and other memory dies in the stack can be connected internally to the stack. The memory dies that are connected externally can act as interface dies for other memory dies that are connected internally thereto. The external connections can be used for transmitting signals indicative of data to and/or from the memory dies while the memory dies in the stack can be connected by a cascading connection for transmission of other signals such as command, address, power, ground, etc.

公开(公告)号：US20220011944A1

公开(公告)日：2022-01-13

申请号：US17349634

申请日：2021-06-16

Applicant: Micron Technology, Inc.

Inventor： Saira Samar Malik ,  Hyunyoo Lee ,  Chinnakrishnan Ballapuram ,  Taeksang Song ,  Kang-Yong Kim

IPC: G06F3/06 ,  G06F12/02

Abstract: Methods, systems, and devices for memory wear management are described. A device may include an interface controller and a non-volatile memory. The interface controller may manage wear-leveling procedures for memory banks in the non-volatile memory. For example, the interface controller may select a row in a memory bank for the wear-leveling procedure. The interface controller may store data from the row in a buffer in the interface controller. The interface controller may then transfer the data to the non-volatile memory so that the non-volatile memory can write the data to a second row of the memory bank.

公开(公告)号：US11074956B1

公开(公告)日：2021-07-27

申请号：US16806942

申请日：2020-03-02

Applicant: Micron Technology, Inc.

Inventor： Huy T. Vo ,  Ferdinando Bedeschi ,  Suryanarayana B. Tatapudi ,  Hyunyoo Lee ,  Adam S. El-Mansouri

IPC: G11C11/22

Abstract: Methods, systems, and devices for an arbitrated sense amplifier are described. A memory device may couple a memory cell to a first node via a digit line and may couple the first node to a second node. If a voltage at the second node is associated with a first logic value stored at the memory cell, the memory device may couple the second node with a third node and may charge the third node according to the voltage. However, if the voltage at the second node is associated with a second logic value stored at the memory cell, the memory device may not couple the second node with the third node. The memory device may compare the resulting voltage at the third node with a reference voltage and may generate a signal indicative of a logic value stored by the memory cell.

公开(公告)号：US20250021875A1

公开(公告)日：2025-01-16

申请号：US18755355

申请日：2024-06-26

Applicant: Micron Technology, Inc.

Inventor： Wonjun Choi ,  Hyunyoo Lee ,  Smruti Subhash Jhaveri

IPC: G06N20/00

Abstract: Test data associated with a command bus training (CBT) can be separately received at interconnected memory dice. Feedback data that are outputted from the multiple interconnected memory dice in response to the test data can be randomly combined such that combined feedback data is returned as if the feedback data were sent from a single memory die. This provides a flexible and scalable architecture that can accommodate a range of memory densities (e.g., a number of memory dice that are interconnected).

公开(公告)号：US12183419B2

公开(公告)日：2024-12-31

申请号：US17648403

申请日：2022-01-19

Applicant: Micron Technology, Inc.

Inventor： Hyunyoo Lee ,  Kang-Yong Kim ,  Taeksang Song

IPC: G11C7/10 ,  G11C8/06 ,  G11C11/4074

Abstract: Methods, systems, and devices for programmable column access are described. A device may transfer voltages from memory cells of a row in a memory array to respective digit lines for the memory cells. The voltages may be indicative of logic values stored at the memory cells. The device may communicate respective control signals to a set of multiplexers coupled with the digit lines, where each multiplexer is coupled with a respective subset of the digit lines. Each multiplexer may couple a digit line of the respective subset of digit lines with a respective sense component for that multiplexer based on the respective control signal for that multiplexer.

公开(公告)号：US20230052489A1

公开(公告)日：2023-02-16

申请号：US17818413

申请日：2022-08-09

Applicant: Micron Technology, Inc.

Inventor： Hyunyoo Lee ,  Kang-Yong Kim ,  Yang Lu

IPC: G11C7/10 ,  H03K19/173 ,  H03K19/017

Abstract: Methods, systems, and devices for die location detection for grouped memory dies are described. A memory device may include multiple memory die that are coupled with a shared bus. In some examples, each memory die may include a circuit configured to output an identifier associated with a location of the respective memory die. For example, a first memory die may output a first identifier, based on receiving one or more signals, that identifies a location of the first memory die. Identifying the locations of the respective memory dies may allow for the dies to be individually accessed despite being coupled with a shared bus.

公开(公告)号：US20220358994A1

公开(公告)日：2022-11-10

申请号：US17662325

申请日：2022-05-06

Applicant: Micron Technology, Inc.

Inventor： Keun Soo Song ,  Hyunyoo Lee ,  Kang Yong Kim

IPC: G11C11/4093 ,  H03K19/00 ,  H03F3/45 ,  G11C11/4076 ,  G06F13/40

Abstract: This document describes apparatuses and techniques for termination for single-ended (SE) mode operation of a memory device. In various aspects, a termination circuit can terminate an unused signal line of a differential pair to a ground or power rail using a switch element when operating in the SE mode. The termination circuit may also disconnect the unused signal line from a first input of a differential amplifier and connect a reference voltage to the first input of the differential amplifier. Based on the reference voltage, the differential amplifier amplifies an SE signal received using another signal line of the differential pair at a second input of the differential amplifier to provide a clock signal for memory operations. Thus, the termination circuit may reduce an amount by which noise associated with the unused signal line affects the differential amplifier when the memory device operates in SE mode.

公开(公告)号：US20220230698A1

公开(公告)日：2022-07-21

申请号：US17647152

申请日：2022-01-05

Applicant: Micron Technology, Inc.

Inventor： Taeksang Song ,  Saira Samar Malik ,  Hyunyoo Lee ,  Chinnakrishnan Ballapuram ,  Kang-Yong Kim

IPC: G11C29/42 ,  G11C29/44 ,  G11C29/12

Abstract: Methods, systems, and devices for centralized error correction circuit are described. An apparatus may include a non-volatile memory disposed on a first die and a volatile memory disposed on a second die (different than the first die). The apparatus may also include an interface controller disposed on a third die (different than the first die and the second die). The interface controller may be coupled with the non-volatile memory and the volatile memory and may include an error correction circuit that is configured to operate on one or more codewords received from the volatile memory.

公开(公告)号：US20210407572A1

公开(公告)日：2021-12-30

申请号：US17338458

申请日：2021-06-03

Applicant: Micron Technology, Inc.

Inventor： Taeksang Song ,  Saira S. Malik ,  Hyunyoo Lee ,  Kang-Yong Kim

IPC: G11C11/4074 ,  H02M3/156 ,  H01L27/108 ,  H01L25/065

Abstract: Methods, systems, and devices for die voltage regulation are described. A device may include a first die and second die. A component that generates voltage on the first die may be connected to a capacitor on the second die through a conductive line. The conductive line may allow the capacitor on the second die to regulate voltage generated by the component on the first die.