公开(公告)号：US20230017305A1

公开(公告)日：2023-01-19

申请号：US17730325

申请日：2022-04-27

Applicant: Micron Technology, Inc.

Inventor： Mattia Cichocki ,  Vladimir Mikhalev ,  Phani Bharadwaj Vanguri ,  James Eric Davis ,  Kenneth William Marr ,  Chiara Cerafogli ,  Michael James Irwin ,  Domenico Tuzi ,  Umberto Siciliani ,  Alessandro Alilla ,  Andrea Giovanni Xotta ,  Chung-Ping Wu ,  Luigi Marchese ,  Pasquale Conenna ,  Joonwoo Nam ,  Ishani Bhatt ,  Fulvio Rori ,  Andrea D'Alessandro ,  Michele Piccardi ,  Aleksey Prozapas ,  Luigi Pilolli ,  Violante Moschiano

IPC: H01L27/02 ,  H01L27/11519 ,  H01L27/11524 ,  H01L27/11529 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/1157 ,  H01L27/11573 ,  H01L27/11582

Abstract: A variety of applications can include apparatus or methods that provide a well ring for resistive ground power domain segregation. The well ring can be implemented as a n-well in a p-type substrate. Resistive separation between ground domains can be generated by biasing a n-well ring to an external supply voltage. This approach can provide a procedure, from a process standpoint, that provides relatively high flexibility to design for chip floor planning and simulation, while providing sufficient noise rejection between independent ground power domains when correctly sized. Significant noise rejection between ground power domains can be attained.

公开(公告)号：US20230005799A1

公开(公告)日：2023-01-05

申请号：US17892749

申请日：2022-08-22

Applicant: Micron Technology, Inc.

Inventor： Chiara Cerafogli ,  Kenneth William Marr ,  Brian J. Soderling ,  Michael P. Violette ,  Joshua Daniel Tomayer ,  James Eric Davis

IPC: H01L21/66 ,  H01L23/00 ,  H01L23/528 ,  H01L27/11526 ,  H01L27/11573 ,  H03K3/03 ,  H01L27/11582 ,  G11C16/26 ,  G11C16/08 ,  G11C16/04 ,  G11C29/14 ,  H01L27/11556

Abstract: Some embodiments include apparatuses and methods of fabricating the apparatuses. One of the apparatuses includes a substrate of a semiconductor die; a memory cell portion located over a first portion of the substrate; a conductive pad portion located over a second portion of the substrate and outside the memory cell portion; and a sensor circuit including a portion located over the second portion of the substrate and under the conductive pad portion. The conductive pad portion includes conductive pads. Each of the conductive pads is part of a respective electrical path coupled to a conductive contact of a base outside the substrate.

公开(公告)号：US20250014665A1

公开(公告)日：2025-01-09

申请号：US18759105

申请日：2024-06-28

Applicant: Micron Technology, Inc.

Inventor： Ivo Thomas Wambeke ,  James Eric Davis ,  Joshua Daniel Tomayer ,  Fulvio Rori ,  Chiara Cerafogli ,  Kenneth William Marr

IPC: G11C29/32 ,  G11C29/12 ,  G11C29/42

Abstract: A memory device can include a first portion having a memory array comprising a plurality of memory cells and a first via chain segment for performing a test operation. The memory device can include a second portion comprising processing circuitry and a second via chain segment for performing the test operation. The memory device can also include an interconnect coupling the first portion and the second portion, the interconnect comprising a third via chain segment, wherein the first via chain segment, second via chain segment, and third via chain segment can be selected independently.

公开(公告)号：US20240233839A9

公开(公告)日：2024-07-11

申请号：US18489770

申请日：2023-10-18

Applicant: Micron Technology, Inc.

Inventor： Chiara Cerafogli ,  Kenneth William Marr ,  Marco Domenico Tiburzi ,  Matthew Joseph Iriondo ,  Warren Lee Boyer ,  Brian James Soderling ,  James Eric Davis ,  Fulvio Rori

IPC: G11C16/32

CPC classification number: G11C16/32 ,  G01K13/00

Abstract: A digital thermometer includes a first oscillator to generate a first clock signal, wherein a period of the first clock signal remains constant in view of changes in a temperature of the apparatus and a first counter coupled to the first oscillator, the first counter to count a fixed number of cycles of the first clock signal associated with a measurement period. The digital thermometer further includes a second oscillator to generate a second clock signal, wherein a period of the second clock signal varies with changes in the temperature and a second counter coupled to the second oscillator, the second counter to generate an output representing a count of a number of cycles of the second clock signal that occur during the measurement period. In addition, the digital thermometer includes calibration circuitry coupled to the second counter, the calibration circuitry to calibrate the output of the second counter to generate a value representing the temperature of the apparatus.

公开(公告)号：US20240136000A1

公开(公告)日：2024-04-25

申请号：US18489770

申请日：2023-10-17

Applicant: Micron Technology, Inc.

Inventor： Chiara Cerafogli ,  Kenneth William Marr ,  Marco Domenico Tiburzi ,  Matthew Joseph Iriondo ,  Warren Lee Boyer ,  Brian James Soderling ,  James Eric Davis ,  Fulvio Rori

IPC: G11C16/32

CPC classification number: G11C16/32 ,  G01K13/00

Abstract: A digital thermometer includes a first oscillator to generate a first clock signal, wherein a period of the first clock signal remains constant in view of changes in a temperature of the apparatus and a first counter coupled to the first oscillator, the first counter to count a fixed number of cycles of the first clock signal associated with a measurement period. The digital thermometer further includes a second oscillator to generate a second clock signal, wherein a period of the second clock signal varies with changes in the temperature and a second counter coupled to the second oscillator, the second counter to generate an output representing a count of a number of cycles of the second clock signal that occur during the measurement period. In addition, the digital thermometer includes calibration circuitry coupled to the second counter, the calibration circuitry to calibrate the output of the second counter to generate a value representing the temperature of the apparatus.