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1.发明申请CONCURRENTLY READING FIRST AND SECOND PAGES OF MEMORY CELLS HAVING DIFFERENT PAGE ADDRESSES 有权同时阅读具有不同页面地址的记忆体的第一页和第二页公开(公告)号：US20170025181A1
公开(公告)日：2017-01-26
申请号：US15288010
申请日：2016-10-07
Applicant: MICRON TECHNOLOGY, INC.
Inventor： Violante Moschiano , Mattia Cichocki , Tommaso Vali , Maria-Luisa Gallese , Umberto Siciliani
IPC: G11C16/26
CPC classification number: G11C16/26 , G11C8/06 , G11C8/12 , G11C11/5642 , G11C16/32
Abstract: In an embodiment, a first page of memory cells in a first memory plane is read concurrently with a second page of memory cells in a second memory plane. The second memory plane is different than the first memory plane, but is in the same memory array as the first memory plane. The second page of memory cells has a different page address than the first page of memory cells.
Abstract translation: 在一个实施例中，第一存储器平面中的第一页存储器单元与第二存储器平面中的第二页存储器单元同时读取。 第二存储器平面与第一存储器平面不同，但是与第一存储器平面处于相同的存储器阵列中。 存储单元的第二页具有与第一页存储单元不同的页地址。
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公开(公告)号：US20180075913A1
公开(公告)日：2018-03-15
申请号：US15722063
申请日：2017-10-02
Applicant: MICRON TECHNOLOGY, INC.
Inventor： Violante Moschiano , Mattia Cichocki , Tommaso Vali , Maria-Luisa Gallese , Umberto Siciliani
CPC classification number: G11C16/26 , G11C8/06 , G11C8/12 , G11C11/5642 , G11C16/32
Abstract: Memory devices may include digital-to-analog converters configured to convert digital values to analog read voltages and to apply the analog read voltages to memory cells in different memory planes, and multiplexers to selectively couple a corresponding table to a page buffer for output of a code from an identified code-containing row of the corresponding tables for each of the different memory planes, with each code corresponding to a data state of one of the memory cells.
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公开(公告)号：US09779826B1
公开(公告)日：2017-10-03
申请号：US15657451
申请日：2017-07-24
Applicant: MICRON TECHNOLOGY, INC.
Inventor： Violante Moschiano , Mattia Cichocki , Tommaso Vali , Maria-Luisa Gallese , Umberto Siciliani
CPC classification number: G11C16/26 , G11C8/06 , G11C8/12 , G11C11/5642 , G11C16/32
Abstract: Memory devices may include digital-to-analog converters configured to convert digital values to analog read voltages and to apply the analog read voltages to memory cells in different memory planes, and multiplexers to selectively couple a corresponding table to a page buffer for output of a code from an identified code-containing row of the corresponding tables for each of the different memory planes, with each code corresponding to a data state of one of the memory cells.
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4.发明授权公开(公告)号：US09754674B2
公开(公告)日：2017-09-05
申请号：US15288010
申请日：2016-10-07
Applicant: MICRON TECHNOLOGY, INC.
Inventor： Violante Moschiano , Mattia Cichocki , Tommaso Vali , Maria-Luisa Gallese , Umberto Siciliani
CPC classification number: G11C16/26 , G11C8/06 , G11C8/12 , G11C11/5642 , G11C16/32
Abstract: In an embodiment, a first page of memory cells in a first memory plane is read concurrently with a second page of memory cells in a second memory plane. The second memory plane is different than the first memory plane, but is in the same memory array as the first memory plane. The second page of memory cells has a different page address than the first page of memory cells.
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公开(公告)号：US09589659B1
公开(公告)日：2017-03-07
申请号：US15164171
申请日：2016-05-25
Applicant: MICRON TECHNOLOGY, INC.
Inventor： Tommaso Vali , Andrea D'Alessandro , Violante Moschiano , Mattia Cichocki , Michele Incarnati , Federica Paolini
CPC classification number: G11C16/3459 , G11C11/5628 , G11C11/5642 , G11C16/0483 , G11C16/10 , G11C16/14 , G11C16/26 , G11C16/3427 , G11C2211/5621 , G11C2211/5648
Abstract: Methods of operating a memory include storing a first target data state of multiple possible data states of a first memory cell to be programmed in a target data latch coupled to a data node, storing at least one bit of a second target data state of the multiple possible data states of a second memory cell to be programmed in an aggressor data latch coupled to the data node, and programming the first memory cell and performing a program verify operation for the first target data state to determine if the first memory cell is verified for the first target data state. The program verify operation including: an intermediate verify corresponding to an amount of aggression to apply a voltage to the data node when performing the intermediate verify, based on the at least one bit of the second target state stored in the aggressor data latch; and a program verify corresponding to a condition of no aggression to apply to the voltage to the data node when performing the program verify, based on the at least one bit of the second target state stored in the aggressor data latch. The methods including inhibiting the first memory cell from further programming if the first memory cell is verified during the intermediate verify and the at least one bit in the aggressor data latch corresponds to the particular amount of aggression, or the first memory cell is verified during the program verify and the at least one bit in the aggressor data latch corresponds to the condition of no aggression. The second memory cell is a neighbor of the first memory cell.
Abstract translation: 操作存储器的方法包括将要编程的第一存储器单元的多个可能数据状态的第一目标数据状态存储在耦合到数据节点的目标数据锁存器中，存储多个第二目标数据状态的至少一位 要在与数据节点耦合的攻击者数据锁存器中编程的第二存储器单元的可能数据状态，以及编程第一存储器单元并对第一目标数据状态执行程序验证操作，以确定第一存储器单元是否被验证 第一个目标数据状态。 所述程序验证操作包括：基于存储在所述侵入者数据锁存器中的所述第二目标状态的所述至少一个位，执行所述中间验证时，对应于所述攻击量的中间验证以向所述数据节点施加电压; 以及基于存储在侵略者数据锁存器中的第二目标状态的至少一个位，在执行程序验证时，对应于不侵略条件的程序验证应用于数据节点的电压。 所述方法包括如果在中间验证期间验证第一存储器单元并且侵略者数据锁存器中的至少一个位对应于特定的侵略量，则禁止第一存储器单元进一步编程，或者在第一存储器单元期间验证第一存储器单元 程序验证，并且攻击者数据锁存中的至少一个位对应于无侵略的条件。 第二存储器单元是第一存储器单元的邻居。
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Patent Agency Ranking
公开(公告)号：US20230017305A1
公开(公告)日：2023-01-19
申请号：US17730325
申请日：2022-04-27
Applicant: Micron Technology, Inc.
Inventor： Mattia Cichocki , Vladimir Mikhalev , Phani Bharadwaj Vanguri , James Eric Davis , Kenneth William Marr , Chiara Cerafogli , Michael James Irwin , Domenico Tuzi , Umberto Siciliani , Alessandro Alilla , Andrea Giovanni Xotta , Chung-Ping Wu , Luigi Marchese , Pasquale Conenna , Joonwoo Nam , Ishani Bhatt , Fulvio Rori , Andrea D'Alessandro , Michele Piccardi , Aleksey Prozapas , Luigi Pilolli , Violante Moschiano
IPC: H01L27/02 , H01L27/11519 , H01L27/11524 , H01L27/11529 , H01L27/11556 , H01L27/11565 , H01L27/1157 , H01L27/11573 , H01L27/11582
Abstract: A variety of applications can include apparatus or methods that provide a well ring for resistive ground power domain segregation. The well ring can be implemented as a n-well in a p-type substrate. Resistive separation between ground domains can be generated by biasing a n-well ring to an external supply voltage. This approach can provide a procedure, from a process standpoint, that provides relatively high flexibility to design for chip floor planning and simulation, while providing sufficient noise rejection between independent ground power domains when correctly sized. Significant noise rejection between ground power domains can be attained.
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公开(公告)号：US10134481B2
公开(公告)日：2018-11-20
申请号：US15449426
申请日：2017-03-03
Applicant: MICRON TECHNOLOGY, INC.
Inventor： Tommaso Vali , Andrea D'Alessandro , Violante Moschiano , Mattia Cichocki , Michele Incarnati , Federica Paolini
Abstract: Methods of operating a memory include storing a first target data state of multiple possible data states of a first memory cell to be programmed in a target data latch coupled to a data node, storing at least one bit of a second target data state of the multiple possible data states of a second memory cell to be programmed in an aggressor data latch coupled to the data node, and programming the first memory cell and performing a program verify operation for the first target data state to determine if the first memory cell is verified for the first target data state. The program verify operation including: an intermediate verify corresponding to an amount of aggression to apply a voltage to the data node when performing the intermediate verify, based on the at least one bit of the second target state stored in the aggressor data latch; and a program verify corresponding to a condition of no aggression to apply to the voltage to the data node when performing the program verify, based on the at least one bit of the second target state stored in the aggressor data latch. The methods including inhibiting the first memory cell from further programming if the first memory cell is verified during the intermediate verify and the at least one bit in the aggressor data latch corresponds to the particular amount of aggression, or the first memory cell is verified during the program verify and the at least one bit in the aggressor data latch corresponds to the condition of no aggression. The second memory cell is a neighbor of the first memory cell.
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公开(公告)号：US10037809B2
公开(公告)日：2018-07-31
申请号：US15722063
申请日：2017-10-02
Applicant: MICRON TECHNOLOGY, INC.
Inventor： Violante Moschiano , Mattia Cichocki , Tommaso Vali , Maria-Luisa Gallese , Umberto Siciliani
CPC classification number: G11C16/26 , G11C8/06 , G11C8/12 , G11C11/5642 , G11C16/32
Abstract: Memory devices may include digital-to-analog converters configured to convert digital values to analog read voltages and to apply the analog read voltages to memory cells in different memory planes, and multiplexers to selectively couple a corresponding table to a page buffer for output of a code from an identified code-containing row of the corresponding tables for each of the different memory planes, with each code corresponding to a data state of one of the memory cells.
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9.发明授权Concurrently reading first and second pages of memory cells having different page addresses 有权同时读取具有不同页面地址的存储单元的第一页和第二页公开(公告)号：US09502125B2
公开(公告)日：2016-11-22
申请号：US14479950
申请日：2014-09-08
Applicant: MICRON TECHNOLOGY, INC.
Inventor： Violante Moschiano , Mattia Cichocki , Tommaso Vali , Maria-Luisa Gallese , Umberto Siciliani
CPC classification number: G11C16/26 , G11C8/06 , G11C8/12 , G11C11/5642 , G11C16/32
Abstract: In an embodiment, a first page of memory cells in a first memory plane is read concurrently with a second page of memory cells in a second memory plane. The second memory plane is different than the first memory plane, but is in the same memory array as the first memory plane. The second page of memory cells has a different page address than the first page of memory cells.
Abstract translation: 在一个实施例中，第一存储器平面中的第一页存储器单元与第二存储器平面中的第二页存储器单元同时读取。 第二存储器平面与第一存储器平面不同，但是与第一存储器平面处于相同的存储器阵列中。 存储单元的第二页具有与第一页存储单元不同的页地址。
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公开(公告)号：US20170345511A1
公开(公告)日：2017-11-30
申请号：US15449426
申请日：2017-03-03
Applicant: MICRON TECHNOLOGY, INC.
Inventor： Tommaso Vali , Andrea D'Alessandro , Violante Moschiano , Mattia Cichocki , Michele Incarnati , Federica Paolini
CPC classification number: G11C16/3459 , G11C11/5628 , G11C11/5642 , G11C16/0483 , G11C16/10 , G11C16/14 , G11C16/26 , G11C16/3427 , G11C2211/5621 , G11C2211/5648
Abstract: Methods of operating a memory include storing a first target data state of multiple possible data states of a first memory cell to be programmed in a target data latch coupled to a data node, storing at least one bit of a second target data state of the multiple possible data states of a second memory cell to be programmed in an aggressor data latch coupled to the data node, and programming the first memory cell and performing a program verify operation for the first target data state to determine if the first memory cell is verified for the first target data state. The program verify operation including: an intermediate verify corresponding to an amount of aggression to apply a voltage to the data node when performing the intermediate verify, based on the at least one bit of the second target state stored in the aggressor data latch; and a program verify corresponding to a condition of no aggression to apply to the voltage to the data node when performing the program verify, based on the at least one bit of the second target state stored in the aggressor data latch. The methods including inhibiting the first memory cell from further programming if the first memory cell is verified during the intermediate verify and the at least one bit in the aggressor data latch corresponds to the particular amount of aggression, or the first memory cell is verified during the program verify and the at least one bit in the aggressor data latch corresponds to the condition of no aggression. The second memory cell is a neighbor of the first memory cell.
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