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1.发明申请CONCURRENTLY READING FIRST AND SECOND PAGES OF MEMORY CELLS HAVING DIFFERENT PAGE ADDRESSES 有权同时阅读具有不同页面地址的记忆体的第一页和第二页公开(公告)号：US20170025181A1
公开(公告)日：2017-01-26
申请号：US15288010
申请日：2016-10-07
Applicant: MICRON TECHNOLOGY, INC.
Inventor： Violante Moschiano , Mattia Cichocki , Tommaso Vali , Maria-Luisa Gallese , Umberto Siciliani
IPC: G11C16/26
CPC classification number: G11C16/26 , G11C8/06 , G11C8/12 , G11C11/5642 , G11C16/32
Abstract: In an embodiment, a first page of memory cells in a first memory plane is read concurrently with a second page of memory cells in a second memory plane. The second memory plane is different than the first memory plane, but is in the same memory array as the first memory plane. The second page of memory cells has a different page address than the first page of memory cells.
Abstract translation: 在一个实施例中，第一存储器平面中的第一页存储器单元与第二存储器平面中的第二页存储器单元同时读取。 第二存储器平面与第一存储器平面不同，但是与第一存储器平面处于相同的存储器阵列中。 存储单元的第二页具有与第一页存储单元不同的页地址。
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公开(公告)号：US10037809B2
公开(公告)日：2018-07-31
申请号：US15722063
申请日：2017-10-02
Applicant: MICRON TECHNOLOGY, INC.
Inventor： Violante Moschiano , Mattia Cichocki , Tommaso Vali , Maria-Luisa Gallese , Umberto Siciliani
CPC classification number: G11C16/26 , G11C8/06 , G11C8/12 , G11C11/5642 , G11C16/32
Abstract: Memory devices may include digital-to-analog converters configured to convert digital values to analog read voltages and to apply the analog read voltages to memory cells in different memory planes, and multiplexers to selectively couple a corresponding table to a page buffer for output of a code from an identified code-containing row of the corresponding tables for each of the different memory planes, with each code corresponding to a data state of one of the memory cells.
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3.发明授权Concurrently reading first and second pages of memory cells having different page addresses 有权同时读取具有不同页面地址的存储单元的第一页和第二页公开(公告)号：US09502125B2
公开(公告)日：2016-11-22
申请号：US14479950
申请日：2014-09-08
Applicant: MICRON TECHNOLOGY, INC.
Inventor： Violante Moschiano , Mattia Cichocki , Tommaso Vali , Maria-Luisa Gallese , Umberto Siciliani
CPC classification number: G11C16/26 , G11C8/06 , G11C8/12 , G11C11/5642 , G11C16/32
Abstract: In an embodiment, a first page of memory cells in a first memory plane is read concurrently with a second page of memory cells in a second memory plane. The second memory plane is different than the first memory plane, but is in the same memory array as the first memory plane. The second page of memory cells has a different page address than the first page of memory cells.
Abstract translation: 在一个实施例中，第一存储器平面中的第一页存储器单元与第二存储器平面中的第二页存储器单元同时读取。 第二存储器平面与第一存储器平面不同，但是与第一存储器平面处于相同的存储器阵列中。 存储单元的第二页具有与第一页存储单元不同的页地址。
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4.发明申请CONCURRENTLY READING FIRST AND SECOND PAGES OF MEMORY CELLS HAVING DIFFERENT PAGE ADDRESSES 有权同时阅读具有不同页面地址的记忆体的第一页和第二页公开(公告)号：US20160071605A1
公开(公告)日：2016-03-10
申请号：US14479950
申请日：2014-09-08
Applicant: MICRON TECHNOLOGY, INC.
Inventor： Violante Moschiano , Mattia Cichocki , Tommaso Vali , Maria-Luisa Gallese , Umberto Siciliani
IPC: G11C16/26
CPC classification number: G11C16/26 , G11C8/06 , G11C8/12 , G11C11/5642 , G11C16/32
Abstract: In an embodiment, a first page of memory cells in a first memory plane is read concurrently with a second page of memory cells in a second memory plane. The second memory plane is different than the first memory plane, but is in the same memory array as the first memory plane. The second page of memory cells has a different page address than the first page of memory cells.
Abstract translation: 在一个实施例中，第一存储器平面中的第一页存储器单元与第二存储器平面中的第二页存储器单元同时读取。 第二存储器平面与第一存储器平面不同，但是与第一存储器平面处于相同的存储器阵列中。 存储单元的第二页具有与第一页存储单元不同的页地址。
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公开(公告)号：US09779839B2
公开(公告)日：2017-10-03
申请号：US14940327
申请日：2015-11-13
Applicant: MICRON TECHNOLOGY, INC.
Inventor： Violante Moschiano , Giovanni Santin , Maria-Luisa Gallese , Luigi Pilolli
CPC classification number: G11C29/846 , G11C16/0483 , G11C29/76 , G11C29/82 , G11C2229/723
Abstract: Methods for providing redundancy in a memory include mapping a portion of first data associated with an address of the memory determined to indicate a defective memory cell to an address of a redundant area of the memory array, and writing second data to the memory array, wherein a portion of the second data is written to a column of the memory array associated with the address of the memory determined to indicate a defective memory cell for the first data.
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Patent Agency Ranking
公开(公告)号：US20160071619A1
公开(公告)日：2016-03-10
申请号：US14940327
申请日：2015-11-13
Applicant: MICRON TECHNOLOGY, INC.
Inventor： Violante Moschiano , Giovanni Santin , Maria-Luisa Gallese , Luigi Pilolli
CPC classification number: G11C29/846 , G11C16/0483 , G11C29/76 , G11C29/82 , G11C2229/723
Abstract: Methods for providing redundancy in a memory include mapping a portion of first data associated with an address of the memory determined to indicate a defective memory cell to an address of a redundant area of the memory array, and writing second data to the memory array, wherein a portion of the second data is written to a column of the memory array associated with the address of the memory determined to indicate a defective memory cell for the first data. Apparatus include memory control circuitry configured to select a portion of data for mapping to a different address in response to an address indicating a defective memory cell, and further configured to select a different portion of data for a particular row than for a different row, wherein the particular row and the different row are associated with the same columns of the memory array.
Abstract translation: 用于在存储器中提供冗余的方法包括将与被确定为指示缺陷存储器单元的存储器的地址相关联的第一数据的一部分映射到存储器阵列的冗余区域的地址，以及将第二数据写入存储器阵列，其中 将第二数据的一部分写入与被确定为指示用于第一数据的有缺陷的存储器单元的存储器的地址相关联的存储器阵列的列。 装置包括存储器控制电路，其被配置为响应于指示有缺陷的存储器单元的地址来选择一部分数据以映射到不同的地址，并且还被配置为为特定行选择不同于不同行的数据的不同部分，其中 特定行和不同行与存储器阵列的相同列相关联。
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公开(公告)号：US09189440B2
公开(公告)日：2015-11-17
申请号：US14330076
申请日：2014-07-14
Applicant: Micron Technology, Inc.
Inventor： Luigi Pilolli , Maria-Luisa Gallese , Mauro Castelli
CPC classification number: G06F13/4027 , G06F12/0607 , G06F2212/254 , G11C11/56 , G11C11/5621 , G11C11/5628
Abstract: The present disclosure includes apparatuses and methods related to a data interleaving module. A number of methods can include interleaving data received from a bus among modules according to a selected one of a plurality of data densities per memory cell supported by an apparatus and transferring the interleaved data from the modules to a register.
Abstract translation: 本公开包括与数据交织模块相关的装置和方法。 许多方法可以包括根据由装置支持的每个存储器单元的多个数据密度中选择的一个，在模块之间交换从总线接收的数据，并将交错的数据从模块传送到寄存器。
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公开(公告)号：US10446258B2
公开(公告)日：2019-10-15
申请号：US15721994
申请日：2017-10-02
Applicant: MICRON TECHNOLOGY, INC.
Inventor： Violante Moschiano , Giovanni Santin , Maria-Luisa Gallese , Luigi Pilolli
Abstract: Methods for providing redundancy in a memory include mapping a portion of first data associated with an address of the memory determined to indicate a defective memory cell to an address of a redundant area of the memory array, and writing second data to the memory array, wherein a portion of the second data is written to a column of the memory array associated with the address of the memory determined to indicate a defective memory cell for the first data. Apparatus include memory control circuitry configured to select a portion of data for mapping to a different address in response to an address indicating a defective memory cell, and further configured to select a different portion of data for a particular row than for a different row, wherein the particular row and the different row are associated with the same columns of the memory array.
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公开(公告)号：US20180075913A1
公开(公告)日：2018-03-15
申请号：US15722063
申请日：2017-10-02
Applicant: MICRON TECHNOLOGY, INC.
Inventor： Violante Moschiano , Mattia Cichocki , Tommaso Vali , Maria-Luisa Gallese , Umberto Siciliani
CPC classification number: G11C16/26 , G11C8/06 , G11C8/12 , G11C11/5642 , G11C16/32
Abstract: Memory devices may include digital-to-analog converters configured to convert digital values to analog read voltages and to apply the analog read voltages to memory cells in different memory planes, and multiplexers to selectively couple a corresponding table to a page buffer for output of a code from an identified code-containing row of the corresponding tables for each of the different memory planes, with each code corresponding to a data state of one of the memory cells.
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公开(公告)号：US20180047460A1
公开(公告)日：2018-02-15
申请号：US15721994
申请日：2017-10-02
Applicant: MICRON TECHNOLOGY, INC.
Inventor： Violante Moschiano , Giovanni Santin , Maria-Luisa Gallese , Luigi Pilolli
CPC classification number: G11C29/846 , G11C16/0483 , G11C29/76 , G11C29/82 , G11C2229/723
Abstract: Methods for providing redundancy in a memory include mapping a portion of first data associated with an address of the memory determined to indicate a defective memory cell to an address of a redundant area of the memory array, and writing second data to the memory array, wherein a portion of the second data is written to a column of the memory array associated with the address of the memory determined to indicate a defective memory cell for the first data. Apparatus include memory control circuitry configured to select a portion of data for mapping to a different address in response to an address indicating a defective memory cell, and further configured to select a different portion of data for a particular row than for a different row, wherein the particular row and the different row are associated with the same columns of the memory array.
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