公开(公告)号：US20210091009A1

公开(公告)日：2021-03-25

申请号：US16579577

申请日：2019-09-23

Applicant: Micron Technology, Inc.

Inventor： Devesh Kumar Datta ,  David Daycock ,  Keen Wah Chow ,  Tom George ,  Justin B. Dorhout ,  Bingli Ma ,  Rita J. Klein ,  John Mark Meldrim

IPC: H01L23/532 ,  H01L23/522 ,  H01L23/528 ,  H01L27/11519 ,  H01L27/11524 ,  H01L27/11565 ,  H01L27/1157

Abstract: Some embodiments include a memory device having a conductive structure which includes silicon-containing material. A stack is over the conductive structure and includes alternating insulative levels and conductive levels. Channel material pillars extend through the stack and are electrically coupled with the conductive structure. Memory cells are along the channel material pillars. A conductive barrier material is under the silicon-containing material. The conductive barrier material includes one or more metals in combination with one or more nonmetals. An electrical contact is under the conductive barrier material. The electrical contact includes a region reactive with silicon. Silicon is precluded from reaching said region at least in part due to the conductive barrier material. Control circuitry is under the electrical contact and is electrically coupled with the conductive structure through at least the electrical contact and the conductive barrier material.

公开(公告)号：US20230343393A1

公开(公告)日：2023-10-26

申请号：US17727487

申请日：2022-04-22

Applicant: Micron Technology, Inc.

Inventor： Jordan D. Greenlee ,  Rajasekhar Venigalla ,  Tom George

IPC: G11C16/04 ,  H01L23/48 ,  H01L27/11519 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/11582

CPC classification number: G11C16/0483 ,  H01L23/481 ,  H01L27/11519 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/11582

Abstract: A method used in forming a memory array comprising strings of memory cells comprises forming a stack comprising vertically-alternating first tiers and second tiers directly above a conductor tier that comprises silicon-containing material. The stack comprises laterally-spaced memory-block regions and a through-array-via (TAV) region. The stack comprises channel-material strings that extend through the first tiers and the second tiers in the memory-block regions. The stack comprises TAV openings in the TAV region that extend to the silicon-containing material of the conductor tier. A metal halide is reacted with the silicon of the silicon-containing material to deposit the metal of the metal halide in the conductor tier. After depositing the metal, conductive material is formed in the TAV openings directly against the deposited metal and therefrom a TAV is formed in individual of the TAV openings that comprises the conductive material and the deposited metal. Structure embodiments are disclosed.

公开(公告)号：US20240071931A1

公开(公告)日：2024-02-29

申请号：US17900064

申请日：2022-08-31

Applicant: Micron Technology, Inc.

Inventor： Tom George ,  Rita J. Klein ,  Daniel Billingsley ,  Pengyuan Zheng ,  Yongjun Jeff Hu

IPC: H01L23/535 ,  H01L27/11556 ,  H01L27/11582

CPC classification number: H01L23/535 ,  H01L27/11556 ,  H01L27/11582

Abstract: A memory array comprising strings of memory cells comprises laterally-spaced memory blocks individually comprising a vertical stack comprising alternating insulative tiers and conductive tiers above a conductor tier. Strings of memory cells comprising channel-material strings extend through the insulative tiers and the conductive tiers. The conductor tier comprises upper conductor material directly above and directly against lower conductor material of different composition from that of the upper conductor material. A through-array-via (TAV) region is included and comprises TAVs individually comprising the upper conductor material, the lower conductor material, and a conducting material that is directly below the conductor tier. The lower conductor material is directly against the conducting material and comprises at least one of (a) and (b), where, (a): a metal-rich refractory metal nitride; and (b): a stoichiometric or non-stoichiometric refractory metal nitride directly above and directly against one of (1), (2), or (3), where: (1): an elemental metal; (2): an alloy of at least two elemental metals; and (3): a metal-rich refractory metal nitride of different composition from that of the stoichiometric or non-stoichiometric refractory metal nitride. Methods are also disclosed.

公开(公告)号：US11177276B2

公开(公告)日：2021-11-16

申请号：US16542675

申请日：2019-08-16

Applicant: Micron Technology, Inc.

Inventor： Nancy M. Lomeli ,  Tom George ,  Jordan D. Greenlee ,  Scott M. Pook ,  John Mark Meldrim

IPC: H01L27/11582 ,  H01L29/10 ,  H01L23/535 ,  G11C16/04 ,  H01L21/768 ,  H01L21/02 ,  G11C16/08 ,  H01L27/11556 ,  H01L27/1157 ,  H01L27/11578 ,  H01L27/11565 ,  H01L29/792 ,  H01L29/788

Abstract: Some embodiments include a conductive structure of an integrated circuit. The conductive structure includes an upper primary portion, with the upper primary portion having a first conductive constituent configured as a container. The container has a bottom, and a pair of sidewalls extending upwardly from the bottom. An interior region of the container is over the bottom and between the sidewalls. The upper primary portion includes a second conductive constituent configured as a mass filling the interior region of the container. The second conductive constituent is a different composition than the first conductive constituent. One or more conductive projections join to the upper primary portion and extend downwardly from the upper primary portion. Some embodiments include assemblies comprising memory cells over conductive structures. Some embodiments include methods of forming conductive structures.

公开(公告)号：US20190198518A1

公开(公告)日：2019-06-27

申请号：US15852955

申请日：2017-12-22

Applicant: Micron Technology, Inc.

Inventor： Nancy M. Lomeli ,  Tom George ,  Jordan D. Greenlee ,  Scott M. Pook ,  John Mark Meldrim

IPC: H01L27/11582 ,  H01L29/10 ,  H01L23/535 ,  G11C16/04 ,  H01L21/768 ,  H01L21/02 ,  H01L27/11556

CPC classification number: H01L27/11582 ,  G11C16/0483 ,  H01L21/02532 ,  H01L21/76807 ,  H01L21/76843 ,  H01L21/76877 ,  H01L23/535 ,  H01L27/11556 ,  H01L29/1037 ,  H01L29/7883 ,  H01L29/7889 ,  H01L29/7926

Abstract: Some embodiments include a conductive structure of an integrated circuit. The conductive structure includes an upper primary portion, with the upper primary portion having a first conductive constituent configured as a container. The container has a bottom, and a pair of sidewalls extending upwardly from the bottom. An interior region of the container is over the bottom and between the sidewalls. The upper primary portion includes a second conductive constituent configured as a mass filling the interior region of the container. The second conductive constituent is a different composition than the first conductive constituent. One or more conductive projections join to the upper primary portion and extend downwardly from the upper primary portion. Some embodiments include assemblies comprising memory cells over conductive structures. Some embodiments include methods of forming conductive structures.

公开(公告)号：US20220415917A1

公开(公告)日：2022-12-29

申请号：US17822708

申请日：2022-08-26

Applicant: Micron Technology, Inc.

Inventor： Daniel Billingsley ,  Matthew J. King ,  Jordan D. Greenlee ,  Yongjun J. Hu ,  Tom George ,  Amritesh Rai ,  Sidhartha Gupta ,  Kyle A. Ritter

IPC: H01L27/11573 ,  H01L27/11582 ,  H01L27/11556 ,  H01L21/28 ,  H01L29/49 ,  H01L27/11529

Abstract: A microelectronic device comprises a stack structure comprising alternating conductive structures and insulative structures arranged in tiers, each of the tiers individually comprising a conductive structure and an insulative structure, strings of memory cells vertically extending through the stack structure, the strings of memory cells comprising a channel material vertically extending through the stack structure, and another stack structure vertically overlying the stack structure and comprising other tiers of alternating levels of other conductive structures and other insulative structures, the other conductive structures exhibiting a conductivity greater than a conductivity of the conductive structures of the stack structure. Related memory devices, electronic systems, and methods are also described.

公开(公告)号：US20220037358A1

公开(公告)日：2022-02-03

申请号：US17502501

申请日：2021-10-15

Applicant: Micron Technology, Inc.

Inventor： Nancy M. Lomeli ,  Tom George ,  Jordan D. Greenlee ,  Scott M. Pook ,  John Mark Meldrim

IPC: H01L27/11582 ,  H01L29/10 ,  H01L23/535 ,  G11C16/04 ,  H01L21/768 ,  H01L21/02 ,  H01L27/11556 ,  H01L27/1157 ,  H01L27/11578 ,  G11C16/08 ,  H01L27/11565

Abstract: Some embodiments include a conductive structure of an integrated circuit. The conductive structure includes an upper primary portion, with the upper primary portion having a first conductive constituent configured as a container. The container has a bottom, and a pair of sidewalls extending upwardly from the bottom. An interior region of the container is over the bottom and between the sidewalls. The upper primary portion includes a second conductive constituent configured as a mass filling the interior region of the container. The second conductive constituent is a different composition than the first conductive constituent. One or more conductive projections join to the upper primary portion and extend downwardly from the upper primary portion. Some embodiments include assemblies comprising memory cells over conductive structures. Some embodiments include methods of forming conductive structures.

公开(公告)号：US10424596B2

公开(公告)日：2019-09-24

申请号：US15852955

申请日：2017-12-22

Applicant: Micron Technology, Inc.

Inventor： Nancy M. Lomeli ,  Tom George ,  Jordan D. Greenlee ,  Scott M. Pook ,  John Mark Meldrim

IPC: H01L27/11582 ,  H01L29/10 ,  H01L23/535 ,  G11C16/04 ,  H01L21/768 ,  H01L21/02 ,  H01L27/11556 ,  H01L29/792 ,  H01L29/788

Abstract: Some embodiments include a conductive structure of an integrated circuit. The conductive structure includes an upper primary portion, with the upper primary portion having a first conductive constituent configured as a container. The container has a bottom, and a pair of sidewalls extending upwardly from the bottom. An interior region of the container is over the bottom and between the sidewalls. The upper primary portion includes a second conductive constituent configured as a mass filling the interior region of the container. The second conductive constituent is a different composition than the first conductive constituent. One or more conductive projections join to the upper primary portion and extend downwardly from the upper primary portion. Some embodiments include assemblies comprising memory cells over conductive structures. Some embodiments include methods of forming conductive structures.

公开(公告)号：US12171101B2

公开(公告)日：2024-12-17

申请号：US17822708

申请日：2022-08-26

Applicant: Micron Technology, Inc.

Inventor： Daniel Billingsley ,  Matthew J. King ,  Jordan D. Greenlee ,  Yongjun J. Hu ,  Tom George ,  Amritesh Rai ,  Sidhartha Gupta ,  Kyle A. Ritter

IPC: H10B41/30 ,  H01L21/28 ,  H01L29/49 ,  H10B41/27 ,  H10B41/41 ,  H10B43/27 ,  H10B43/30 ,  H10B43/40

Abstract: A microelectronic device comprises a stack structure comprising alternating conductive structures and insulative structures arranged in tiers, each of the tiers individually comprising a conductive structure and an insulative structure, strings of memory cells vertically extending through the stack structure, the strings of memory cells comprising a channel material vertically extending through the stack structure, and another stack structure vertically overlying the stack structure and comprising other tiers of alternating levels of other conductive structures and other insulative structures, the other conductive structures exhibiting a conductivity greater than a conductivity of the conductive structures of the stack structure. Related memory devices, electronic systems, and methods are also described.

公开(公告)号：US11527546B2

公开(公告)日：2022-12-13

申请号：US16943826

申请日：2020-07-30

Applicant: Micron Technology, Inc.

Inventor： Daniel Billingsley ,  Matthew J. King ,  Jordan D. Greenlee ,  Yongjun J. Hu ,  Tom George ,  Amritesh Rai ,  Sidhartha Gupta ,  Kyle A. Ritter

IPC: H01L27/11556 ,  H01L27/11573 ,  H01L27/11582 ,  H01L21/28 ,  H01L29/49 ,  H01L27/11529

Abstract: A microelectronic device comprises a stack structure comprising alternating conductive structures and insulative structures arranged in tiers, each of the tiers individually comprising a conductive structure and an insulative structure, strings of memory cells vertically extending through the stack structure, the strings of memory cells comprising a channel material vertically extending through the stack structure, and another stack structure vertically overlying the stack structure and comprising other tiers of alternating levels of other conductive structures and other insulative structures, the other conductive structures exhibiting a conductivity greater than a conductivity of the conductive structures of the stack structure. Related memory devices, electronic systems, and methods are also described.