公开(公告)号：US20240289218A1

公开(公告)日：2024-08-29

申请号：US18586048

申请日：2024-02-23

Applicant: Micron Technology, Inc.

Inventor： David Ebsen ,  Kishore Kumar Muchherla ,  James Fitzpatrick ,  Dung V. Nguyen ,  Kevin R. Brandt ,  Vikas Rana ,  William Richard Akin

IPC: G06F11/10 ,  G06F13/16

CPC classification number: G06F11/1068 ,  G06F11/1004 ,  G06F13/1673

Abstract: Data is read from a set of memory cells of a memory device to a buffer of the memory device. One or more bits in error in the data stored by the buffer are corrected by a decoder of the memory device. The decoder corrects the one or more bits in error by decoding the data stored by the buffer. The decoding of the data results in corrected data. An encoder of the memory device encodes the corrected data and the encoded corrected data is programmed to the set of memory cells.

公开(公告)号：US20240070059A1

公开(公告)日：2024-02-29

申请号：US17898604

申请日：2022-08-30

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Vikas Rana ,  Kalyan Chakravarthy Kavalipurapu

IPC: G06F12/02 ,  G06F11/10 ,  G11C16/04 ,  G11C16/08 ,  G11C16/24 ,  G11C16/26

CPC classification number: G06F12/0238 ,  G06F11/1044 ,  G11C16/0483 ,  G11C16/08 ,  G11C16/24 ,  G11C16/26 ,  G06F2212/202

Abstract: A memory device includes a first array of Non-Volatile Memory (NVM) cells, a second array of logic NVM cells, and a controller. The second array of logic NVM cells stores instructions for accessing the first array of NVM cells. The controller is configured to execute the instructions stored in the second array of logic NVM cells to perform access operations in the first array of NVM cells.

公开(公告)号：US20230325085A1

公开(公告)日：2023-10-12

申请号：US18117553

申请日：2023-03-06

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Vikas Rana ,  Kalyan Chakravarthy Kavalipurapu

IPC: G06F3/06 ,  G11C16/04 ,  G11C16/10 ,  G11C16/24 ,  G11C16/26

CPC classification number: G06F3/061 ,  G06F3/0659 ,  G06F3/0679 ,  G06F3/0656 ,  G11C16/0483 ,  G11C16/10 ,  G11C16/24 ,  G11C16/26

Abstract: Memory might include an array of memory cells and a data line selectively connected to a plurality of memory cells of the array of memory cells. The data line might include a first data line segment corresponding to a first subset of memory cells of the plurality of memory cells and a second data line segment corresponding to a second subset of memory cells of the plurality of memory cells. The second data line segment is selectively connected to the first data line segment. A first page buffer might be selectively connected to the first data line segment, and a second page buffer might be selectively connected to the second data line segment.