公开(公告)号：US11201113B2

公开(公告)日：2021-12-14

申请号：US16523277

申请日：2019-07-26

Applicant: NXP B.V.

Inventor： Olivier Tesson

IPC: H01L23/522 ,  H01L21/768 ,  H01L23/528

Abstract: An integrated circuit comprising a semiconductor substrate and a passive coupler located on the substrate. The coupler includes a solenoid. The coupler also includes a signal line passing through the solenoid. A method of making an integrated circuit. The method includes providing a semiconductor substrate and forming a passive coupler in a metallization stack on the substrate. Forming the passive coupler in the metallization stack on the substrate includes forming one or more windings of the solenoid using patterned metal features in a plurality of metal layers of the metallization stack. Forming the passive coupler in the metallization stack on the substrate also includes forming a signal line using one or more patterned metal features in one or more metal layers of the metallization stack. The signal line passes through the solenoid.

公开(公告)号：US09391214B2

公开(公告)日：2016-07-12

申请号：US14635018

申请日：2015-03-02

Applicant: NXP B.V.

Inventor： Olivier Tesson ,  Mathieu Perin ,  Laure Rolland du Roscoat

IPC: H01L29/93 ,  H03B5/12 ,  H01L29/66 ,  H01L27/08 ,  H01L29/94 ,  H01L29/423 ,  H01L23/482

CPC classification number: H01L29/93 ,  H01L23/4824 ,  H01L27/0808 ,  H01L27/0811 ,  H01L29/423 ,  H01L29/66174 ,  H01L29/94 ,  H01L2924/0002 ,  H03B5/124 ,  H03B5/1243 ,  H01L2924/00

Abstract: A MOS varactor structure comprising a semiconductor body having a well region and a plurality of gate electrodes and a plurality of cathode electrodes arranged over the well region, wherein the gate electrodes comprise elongate pads, and the plurality of cathode contacts are connected by a cathode connection pattern, the cathode connection pattern comprising a plurality of arms, each of the plurality of arms arranged to extend over a part of a respective gate electrode pad.

Abstract translation: 一种MOS变容二极管结构，包括具有阱区和多个栅电极的半导体本体和布置在阱区上的多个阴极，其中栅电极包括细长焊盘，并且多个阴极触点通过阴极连接 阴极连接图案包括多个臂，所述多个臂中的每一个布置成在相应的栅电极焊盘的一部分上延伸。

公开(公告)号：US12009565B2

公开(公告)日：2024-06-11

申请号：US17314219

申请日：2021-05-07

Applicant: NXP B.V.

Inventor： Olivier Tesson ,  Mustafa Acar

IPC: H03H7/46 ,  H01L23/66 ,  H01P5/16 ,  H01P11/00

CPC classification number: H01P5/16 ,  H01L23/66 ,  H01P11/003 ,  H03H7/461 ,  H01L2223/6627

Abstract: A power combiner/splitter for multiple input multiple output (MIMO) applications and a method of making the same. A metallisation stack has a plurality of layers including patterned metal features forming first and second branched arrangements of the power combiner/splitter. Each branched arrangement includes a port located at one end of that branched arrangement, and a plurality of further ports. Each branched arrangement also includes a plurality of bifurcated branches extending between each end of that branched arrangement for dividing/combining a signal passing through that branched arrangement between the port and the plurality of further ports. The metallisation stack further includes a common ground plane that is shared by the first and second branched arrangements. At least some of the patterned metal features forming the first branched arrangement overlie at least some of the patterned metal features forming the second branched arrangement.

公开(公告)号：US20230170851A1

公开(公告)日：2023-06-01

申请号：US18056767

申请日：2022-11-18

Applicant: NXP B.V.

Inventor： Adam Erik Waks ,  Olivier Tesson ,  Olivier Crand

IPC: H03F1/32 ,  H03H11/20

CPC classification number: H03F1/3247 ,  H03H11/20 ,  H03F2200/451

Abstract: A phase shifter (100) with controllable attenuation and a method for controlling the phase shifter is disclosed, the phase shifter (100) comprising a plurality of transmission line segments (120, 220) coupled in series, wherein each said transmission line segment (120, 220) comprises an attenuation circuit (130, 230), selectively couplable between a signal line (126, 222) of the transmission line segment (120, 220) and ground to selectively attenuate a signal propagating through the transmission line segment (120, 220). Each transmission line segment (120, 220) is switchable between a first configuration providing a first phase shift for a signal propagating through the transmission line segment (120, 220) and a second configuration providing a second phase shift, greater than said first phase shift, for a signal propagating through the transmission line segment (120, 220).

公开(公告)号：US10217671B2

公开(公告)日：2019-02-26

申请号：US15865867

申请日：2018-01-09

Applicant: NXP B.V.

Inventor： Olivier Tesson ,  Thomas Francois

IPC: H01L29/06 ,  H01L29/66 ,  H01L29/78 ,  H01L21/762 ,  H01L23/482 ,  H01L29/417 ,  H01L29/423 ,  H01L21/8234

Abstract: A semiconductor device comprising a switch and a method of making the same. The device, has a layout having one or more rectangular unit cells. Each unit cell includes a gate having a substantially cross-shaped part comprising four arms that divide the unit cell into quadrants; and a substantially loop-shaped part, wherein a center of the cross-shaped part is located inside the loop-shaped part, and wherein the loop-shaped part intersects each arm of the cross-shaped part to divide each quadrant into an inner region located inside the loop-shaped part; and an outer region located outside the loop-shaped part. Each unit cell also includes a substantially loop-shaped active region forming a source and drain of the switch. Each unit cell further includes a plurality of connection members extending over the gate, source and drain for providing electrical connections to the source and drain.

公开(公告)号：US09704647B2

公开(公告)日：2017-07-11

申请号：US14680699

申请日：2015-04-07

Applicant: NXP B.V.

Inventor： Magali Duplessis ,  Olivier Tesson

IPC: H01F5/00 ,  H01F41/06 ,  H01F17/00 ,  H01F27/34 ,  H01F41/04 ,  H01L23/522 ,  H01F27/28 ,  B23K1/00 ,  B23K1/20 ,  C23C14/02 ,  C23C14/14 ,  C25D3/38 ,  C25D5/02

CPC classification number: H01F41/06 ,  B23K1/0016 ,  B23K1/20 ,  C23C14/021 ,  C23C14/14 ,  C25D3/38 ,  C25D5/02 ,  H01F5/00 ,  H01F17/0006 ,  H01F27/2895 ,  H01F27/34 ,  H01F41/041 ,  H01F2017/0086 ,  H01L23/5227 ,  H01L2924/0002 ,  Y10T29/49071 ,  H01L2924/00

Abstract: A transformer comprising primary and secondary windings is disclosed. Each winding has first and second metal capping layers coupled together electrically in parallel by a metal connector passing through a substrate lying between the first and second metal capping layers.

公开(公告)号：US09160052B2

公开(公告)日：2015-10-13

申请号：US13781564

申请日：2013-02-28

Applicant: NXP B.V.

Inventor： Olivier Tesson ,  Patrice Gamand ,  Sidina Wane

IPC: H01P5/18

CPC classification number: H01P5/186

Abstract: A Lange coupler comprises an unbroken peripheral ground conductor surrounding input, through, coupled and isolated conductor strips coupled to input, through, coupled and isolated ports of the Lange coupler respectively, wherein the peripheral ground conductor and input and through conductor strips are arranged on a first metal layer.

Abstract translation: Lange耦合器包括一个不间断的外围接地导体，其围绕分别耦合到兰格耦合器的输入，通过，耦合和隔离端口的输入，通过，耦合和隔离的导体条，其中外围接地导体和输入和通过导体条布置在 第一金属层。

公开(公告)号：US09136061B2

公开(公告)日：2015-09-15

申请号：US13953539

申请日：2013-07-29

Applicant: NXP B.V.

Inventor： Olivier Tesson ,  Laure Rolland du Roscoat

IPC: H01L29/93 ,  H01G7/06 ,  H01L27/08 ,  H01L23/482 ,  H01L29/66 ,  H01L27/02 ,  H01L49/02

CPC classification number: H01G7/06 ,  H01L23/4824 ,  H01L27/0207 ,  H01L27/0808 ,  H01L27/0811 ,  H01L28/86 ,  H01L29/66174 ,  H01L29/93 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A varactor comprises a substrate having sets of gate units each having parallel gate strips. The gate units are located such that the gate strips of neighboring gate units are oriented transverse to each other. An electrically conducting gate connection layer comprises gate connection units comprising parallel gate connection strips located over the gate strips, and a cathode connection frame around each of the gate connection units. A first electrically conductive anode layer comprises first layer anode strips located parallel to the gate connection strips and connected to alternate gate connection strips, and a first anode connection frame connected to the anode strips. A second electrically conductive anode layer comprises anode strips located parallel to the gate connection strips and connected to opposite alternate gate connection strips, and a second anode connection frame connected to the second layer anode strips.

Abstract translation: 变容二极管包括具有各自具有平行栅极条的栅极单元组的衬底。 栅极单元被定位成使得相邻栅极单元的栅极条彼此横向定向。 导电栅极连接层包括栅极连接单元，栅极连接单元包括位于栅极条上的并联栅极连接条，以及围绕每个栅极连接单元的阴极连接框架。 第一导电阳极层包括平行于栅极连接条并连接到交替栅极连接条的第一层阳极条和连接到阳极条的第一阳极连接框架。 第二导电阳极层包括平行于栅极连接条并连接到相对的交替栅极连接条的阳极条，以及连接到第二层阳极条的第二阳极连接框架。

公开(公告)号：US20240120148A1

公开(公告)日：2024-04-11

申请号：US18476360

申请日：2023-09-28

Applicant: NXP B.V.

Inventor： Vinicius Azevedo de Souza e Vecchia ,  Stephane David ,  Olivier Tesson

IPC: H01F30/02

CPC classification number: H01F30/02

Abstract: There is provided a phase shifting device and method of manufacturing the same. The device comprises an auto-transformer comprising a primary winding configured to receive an input signal; and two secondary windings, wherein a first one of the two secondary windings is in phase with the primary winding and a second one of the two secondary windings is out of phase with the primary winding. The device also comprises a first switch coupled to an output signal of the first one of the two secondary windings of the auto-transformer; and a second switch coupled to an output signal of the second one of the two secondary windings of the auto-transformer. Output signals of the first and second switches are couplable to an output of the phase shifting device.

公开(公告)号：US20210359388A1

公开(公告)日：2021-11-18

申请号：US17314219

申请日：2021-05-07

Applicant: NXP B.V.

Inventor： Olivier Tesson ,  Mustafa Acar

IPC: H01P5/16 ,  H01L23/66 ,  H01P11/00

Abstract: A power combiner/splitter for multiple input multiple output (MIMO) applications and a method of making the same. A metallisation stack has a plurality of layers including patterned metal features forming first and second branched arrangements of the power combiner/splitter. Each branched arrangement includes a port located at one end of that branched arrangement, and a plurality of further ports. Each branched arrangement also includes a plurality of bifurcated branches extending between each end of that branched arrangement for dividing/combining a signal passing through that branched arrangement between the port and the plurality of further ports. The metallisation stack further includes a common ground plane that is shared by the first and second branched arrangements. At least some of the patterned metal features forming the first branched arrangement overlie at least some of the patterned metal features forming the second branched arrangement.