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    AUTO-LINKING OF FUNCTION LOGIC STATE WITH TESTCASE REGRESSION LIST
    1.
    发明申请
    AUTO-LINKING OF FUNCTION LOGIC STATE WITH TESTCASE REGRESSION LIST 失效
    功能状态与TESTCASE回归列表的自动连接

    公开(公告)号：US20050096862A1

    公开(公告)日：2005-05-05

    申请号：US10605884

    申请日：2003-11-04

    申请人： Jason Norman ,  Nancy Pratt ,  Sebastian Ventrone

    发明人： Jason Norman ,  Nancy Pratt ,  Sebastian Ventrone

    IPC分类号： G01R31/14 ,  G06F11/26

    CPC分类号： G06F11/261

    摘要： A method and system for identifying logic function areas, which make up a virtual machine, that are affected by specific testcases. A Hardware Descriptor Language (HDL) is used to create a software model of the virtual machine. A simulator compiles and analyzes the HDL model, and creates a matrix scoreboard identifying logic function areas in the virtual machine. A complete list of testcases is run on the virtual machine while a monitor correlates each testcase with affected logic function areas to fill in the matrix scoreboard. When a subsequent test failure occurs, either because of a modification to a logic function area, or the execution of a new test, all logic function areas that are affected, either directly or indirectly, are identified.

    摘要翻译： 用于识别构成虚拟机的逻辑功能区域受到特定测试用例影响的方法和系统。 硬件描述符语言（HDL）用于创建虚拟机的软件模型。 模拟器编译和分析HDL模型，并创建一个标识虚拟机中逻辑功能区域的矩阵记分板。 测试用例的完整列表在虚拟机上运行，​​而监视器将每个测试用例与受影响的逻辑功能区域相关联，以填充矩阵记分板。 当随后的测试失败发生时，由于对逻辑功能区域的修改或新测试的执行，所有被直接或间接影响的逻辑功能区域都被识别。

    NOISE REDUCTION IN DIGITAL SYSTEMS
    2.
    发明申请
    NOISE REDUCTION IN DIGITAL SYSTEMS 失效
    数字系统中的噪声减少

    公开(公告)号：US20080068073A1

    公开(公告)日：2008-03-20

    申请号：US11937559

    申请日：2007-11-09

    申请人： Nancy Pratt ,  Sebastian Ventrone

    发明人： Nancy Pratt ,  Sebastian Ventrone

    IPC分类号： H03K5/00

    CPC分类号： G06F1/04 ,  H03K5/1504 ,  H03K19/00361

    摘要： A digital system. The digital system includes (a) a first logic circuit and a second logic circuit, (b) a first register, (c) a second register, (d) a third register, (e) a clock generator circuit, and (f) a controller circuit. The first logic circuit is capable of obtaining first data and sending second data. The second logic circuit is capable of obtaining the second data and sending third data. The clock generator circuit is capable of asserting (i) a first register clock signal at a first time point, (ii) a second register clock signal at a second time point, and (iii) a third register clock signal at a third time point. The controller circuit is capable of (i) determining a fourth time point, (ii) determining a fifth time point, (iii) controlling the clock generator circuit to assert the second register clock signal.

    摘要翻译： 数字系统 数字系统包括（a）第一逻辑电路和第二逻辑电路，（b）第一寄存器，（c）第二寄存器，（d）第三寄存器，（e）时钟发生器电路，以及（f） 一个控制器电路。 第一逻辑电路能够获得第一数据并发送第二数据。 第二逻辑电路能够获得第二数据并发送第三数据。 时钟发生器电路能够在第一时间点断言（i）第一寄存器时钟信号，（ii）在第二时间点的第二寄存器时钟信号，以及（iii）第三时间点的第三寄存器时钟信号 。 控制器电路能够（i）确定第四时间点，（ii）确定第五时间点，（iii）控制时钟发生器电路以断言第二寄存器时钟信号。

    NOISE REDUCTION IN DIGITAL SYSTEMS
    3.
    发明申请
    NOISE REDUCTION IN DIGITAL SYSTEMS 审中-公开
    数字系统中的噪声减少

    公开(公告)号：US20070288787A1

    公开(公告)日：2007-12-13

    申请号：US11836827

    申请日：2007-08-10

    申请人： Nancy Pratt ,  Sebastian Ventrone

    发明人： Nancy Pratt ,  Sebastian Ventrone

    IPC分类号： G06F1/00

    CPC分类号： G06F1/04 ,  H03K5/1504 ,  H03K19/00361

    摘要： A digital system and a method for operating the same. The digital system includes (a) a first logic circuit and a second logic circuit, (b) a first register, (c) a second register, (d) a third register, (e) a clock generator circuit, and (f) a controller circuit. The first logic circuit is capable of obtaining first data and sending second data. The second logic circuit is capable of obtaining the second data and sending third data. The clock generator circuit is capable of asserting (i) a first register clock signal at a first time point, (ii) a second register clock signal at a second time point, and (iii) a third register clock signal at a third time point. The controller circuit is capable of (i) determining a fourth time point, (ii) determining a fifth time point, (iii) controlling the clock generator circuit to assert the second register clock signal.

    摘要翻译： 数字系统及其操作方法。 数字系统包括（a）第一逻辑电路和第二逻辑电路，（b）第一寄存器，（c）第二寄存器，（d）第三寄存器，（e）时钟发生器电路，以及（f） 一个控制器电路。 第一逻辑电路能够获得第一数据并发送第二数据。 第二逻辑电路能够获得第二数据并发送第三数据。 时钟发生器电路能够在第一时间点断言（i）第一寄存器时钟信号，（ii）在第二时间点的第二寄存器时钟信号，以及（iii）第三时间点的第三寄存器时钟信号 。 控制器电路能够（i）确定第四时间点，（ii）确定第五时间点，（iii）控制时钟发生器电路以断言第二寄存器时钟信号。

    SUPERVISORY OPERATING SYSTEM FOR RUNNING MULTIPLE CHILD OPERATING SYSTEMS SIMULTANEOUSLY AND OPTIMIZING RESOURCE USAGE
    4.
    发明申请
    SUPERVISORY OPERATING SYSTEM FOR RUNNING MULTIPLE CHILD OPERATING SYSTEMS SIMULTANEOUSLY AND OPTIMIZING RESOURCE USAGE 有权
    监督操作系统，用于同时运行多个儿童操作系统并优化资源使用

    公开(公告)号：US20070028151A1

    公开(公告)日：2007-02-01

    申请号：US11161330

    申请日：2005-07-29

    申请人： Laura Miller ,  Nancy Pratt ,  Sebastian Ventrone

    发明人： Laura Miller ,  Nancy Pratt ,  Sebastian Ventrone

    IPC分类号： G06F11/00

    CPC分类号： G06F9/462 ,  G06F9/4843

    摘要： A method and system for supporting simultaneous operation of operating systems on a single integrated circuit. The system includes a supervisory operating system (SOS) managing execution of instructions, each instruction being executable under one of the operating systems; registers grouped into multiple sets of registers, each set maintaining an identity of one of the operating systems; and a dispatcher capable of dispatching an instruction and a tag attached to the instruction, the tag identifying one of the operating systems and the instruction to be executed under the identified operating system to access one of the registers. One or more of the registers are utilized when the instruction is executed, and are included in a single set of the multiple sets of registers. The single set maintains the identity of the operating system identified by the tag, and each of the one or more registers includes an identifier matching the tag.

    摘要翻译： 一种用于在单个集成电路上支持同时操作操作系统的方法和系统。 该系统包括管理指令的执行的监控操作系统（SOS），每个指令可在一个操作系统下执行; 寄存器分组成多组寄存器，每组寄存器保持一个操作系统的标识; 以及调度器，其能够分派附加到所述指令的指令和标签，所述标签识别所述操作系统中的一个以及在所述操作系统下执行的指令以访问所述寄存器之一。 当执行指令时，使用一个或多个寄存器，并且被包括在多组寄存器的单组中。 单一集合维护由标签识别的操作系统的标识，并且一个或多个寄存器中的每一个包括与标签相匹配的标识符。

    NOISE REDUCTION IN DIGITAL SYSTEMS
    5.
    发明申请
    NOISE REDUCTION IN DIGITAL SYSTEMS 失效
    数字系统中的噪声减少

    公开(公告)号：US20060082398A1

    公开(公告)日：2006-04-20

    申请号：US11275773

    申请日：2006-01-27

    申请人： Nancy Pratt ,  Sebastian Ventrone

    发明人： Nancy Pratt ,  Sebastian Ventrone

    IPC分类号： H03B21/00

    CPC分类号： G06F1/04 ,  H03K5/1504 ,  H03K19/00361

    摘要： A digital system and a method for operating the same. The digital system includes (a) a first logic circuit and a second logic circuit, (b) a first register, (c) a second register, (d) a third register, (e) a clock generator circuit, and (f) a controller circuit. The first logic circuit is capable of obtaining first data and sending second data. The second logic circuit is capable of obtaining the second data and sending third data. The clock generator circuit is capable of asserting (i) a first register clock signal at a first time point, (ii) a second register clock signal at a second time point, and (iii) a third register clock signal at a third time point. The controller circuit is capable of (i) determining a fourth time point, (ii) determining a fifth time point, (iii) controlling the clock generator circuit to assert the second register clock signal.

    摘要翻译： 数字系统及其操作方法。 数字系统包括（a）第一逻辑电路和第二逻辑电路，（b）第一寄存器，（c）第二寄存器，（d）第三寄存器，（e）时钟发生器电路，以及（f） 一个控制器电路。 第一逻辑电路能够获得第一数据并发送第二数据。 第二逻辑电路能够获得第二数据并发送第三数据。 时钟发生器电路能够在第一时间点断言（i）第一寄存器时钟信号，（ii）在第二时间点的第二寄存器时钟信号，以及（iii）第三时间点的第三寄存器时钟信号 。 控制器电路能够（i）确定第四时间点，（ii）确定第五时间点，（iii）控制时钟发生器电路以断言第二寄存器时钟信号。

    FPGA POWERUP TO KNOWN FUNCTIONAL STATE
    6.
    发明申请
    FPGA POWERUP TO KNOWN FUNCTIONAL STATE 失效
    FPGA电源到已知的功能状态

    公开(公告)号：US20080030226A1

    公开(公告)日：2008-02-07

    申请号：US11869921

    申请日：2007-10-10

    申请人： Kenneth Goodnow ,  Clarence Ogilvie ,  Christopher Reynolds ,  Jack Smith ,  Sebastian Ventrone ,  Keith Williams

    发明人： Kenneth Goodnow ,  Clarence Ogilvie ,  Christopher Reynolds ,  Jack Smith ,  Sebastian Ventrone ,  Keith Williams

    IPC分类号： H03K19/173

    CPC分类号： H03K19/17776 ,  H03K19/17732 ,  H03K19/17756 ,  H03K19/17772

    摘要： A field programmable gate array (FPGA) device including a non-non-programming-based default power-on electronic configuration. The non-non-programming-based default power-on electronic configuration defines a default state to initial a first logic function. Upon power-up, the FPGA device would be enabled to enter the default state without having first to be configured via a conventional programming mode, thus saving precious processing time during power-up. Several embodiments are disclosed, such as a mask via circuit, an asynchronized set/reset circuit, an unbalanced latch circuit and a flush and scan circuit. A related method is also disclosed to reduce the memory size dedicated to the first logic function to facilitate further programming after power-up. In addition to time saving and further programming, the FPGA device can also allow partial or incremental programming to expand the full functionality to match customer's different needs.

    摘要翻译： 包括非基于非编程的默认开机电子配置的现场可编程门阵列（FPGA）设备。 非基于非编程的默认开机电子配置定义了初始化第一逻辑功能的默认状态。 上电时，FPGA器件将能够进入默认状态，而不必首先通过常规编程模式进行配置，从而在上电时节省宝贵的处理时间。 公开了几个实施例，例如掩模通孔电路，异步设置/复位电路，不平衡锁存电路和冲洗和扫描电路。 还公开了一种相关方法，以减少专用于第一逻辑功能的存储器大小，以便在上电之后进一步编程。 除了节省时间和进一步的编程之外，FPGA器件还可以允许部分或增量编程扩展完整的功能以满足客户的不同需求。

    DETERMINING RELATIVE AMOUNT OF USAGE OF DATA RETAINING DEVICE BASED ON POTENTIAL OF CHARGE STORING DEVICE
    7.
    发明申请
    DETERMINING RELATIVE AMOUNT OF USAGE OF DATA RETAINING DEVICE BASED ON POTENTIAL OF CHARGE STORING DEVICE 有权
    基于充电储存装置的可能性确定使用数据保留装置的相对数量

    公开(公告)号：US20070258305A1

    公开(公告)日：2007-11-08

    申请号：US11279639

    申请日：2006-04-13

    申请人： Kerry Bernstein ,  Kenneth Goodnow ,  Clarence Ogilvie ,  Sebastian Ventrone ,  Keith Williams

    发明人： Kerry Bernstein ,  Kenneth Goodnow ,  Clarence Ogilvie ,  Sebastian Ventrone ,  Keith Williams

    IPC分类号： G11C7/00

    CPC分类号： G06F12/121 ,  G06F12/122

    摘要： A system, method and program product for determining a relative amount of usage of a data retaining device are disclosed. A charge storing device is coupled to a data retaining device in a manner that a use of the data retaining device triggers a charging of the charge storing device. In a period that the data retaining device idles, charges in the charge storing device decay due to natural means. As such, a potential of the charge storing device may be used to indicate an amount of usage of the data retaining device. A comparison of the potentials of two charge storing devices coupled one-to-one to two data retaining devices may be used as a basis to determine a relative amount of usage of each of the two data retaining devices comparing to the other.

    摘要翻译： 公开了一种用于确定数据保留装置的相对使用量的系统，方法和程序产品。 电荷存储装置以数据保持装置的使用触发电荷存储装置的充电的方式耦合到数据保持装置。 在数据保持装置闲置的期间，由于自然的手段，电荷存储装置中的电荷衰减。 因此，可以使用电荷存储装置的电位来指示数据保持装置的使用量。 可以使用将一对一耦合到两个数据保持装置的两个电荷存储装置的电位的比较作为确定两个数据保持装置中的每一个相对于另一个的相对使用量的基础。

    Coding of FPGA and standard cell logic in a tiling structure
    10.
    发明申请
    Coding of FPGA and standard cell logic in a tiling structure 审中-公开
    FPGA和标准单元逻辑在平铺结构中的编码

    公开(公告)号：US20060190908A1

    公开(公告)日：2006-08-24

    申请号：US11375891

    申请日：2006-03-15

    申请人： Stanislav Bajuk ,  Jack Smith ,  Sebastian Ventrone

    发明人： Stanislav Bajuk ,  Jack Smith ,  Sebastian Ventrone

    IPC分类号： G06F17/50

    CPC分类号： G06F17/5045 ,  G06F17/5068

    摘要： A method and system for storing and modifying register transfer language (RTL) described logic types. Upon a declaration of a signal interconnect, a language extension of a register transfer language is defined for the signal interconnect based on the signal interconnect”s type. The language extensions allow different signal interconnect types, such as those used with field programmable gate arrays (FPGA) and standard cells, to be stored in a same file array hierarchy. This storage facilitates changing logic types, thus ultimately resulting in an integrated circuit (IC) that is either smaller (using more standard cells) or more flexible (using more FPGA cells). The transition from one RTL type to another is performed within the physical design cycle, in which wiring, timing and placement of components (information) is performed before masking out the final chip design.

    摘要翻译： 一种存储和修改寄存器传输语言（RTL）的方法和系统，描述逻辑类型。 在声明信号互连时，基于信号互连的类型为信号互连定义了寄存器传输语言的语言扩展。语言扩展允许不同的信号互连类型，例如与现场可编程门阵列（例如， FPGA）和标准单元存储在相同的文件阵列层次结构中，这种存储有助于改变逻辑类型，从而最终导致集成电路（IC）更小（使用更多的标准单元）或更灵活（使用更多的FPGA 在物理设计周期内执行从一个RTL类型到另一个RTL类型的转换，其中在屏蔽最终芯片设计之前执行组件（信息）的布线，定时和布局。