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    REDUCING CACHE COHERENCY DIRECTORY BANDWIDTH BY AGGREGATING VICTIMIZATION REQUESTS
    1.
    发明申请
    REDUCING CACHE COHERENCY DIRECTORY BANDWIDTH BY AGGREGATING VICTIMIZATION REQUESTS 审中-公开
    通过聚集维权要求减少高速缓存目录带宽

    公开(公告)号：US20170060745A1

    公开(公告)日：2017-03-02

    申请号：US14834628

    申请日：2015-08-25

    Applicant: Oracle International Corporation

    Inventor： Thomas Wicki ,  Jurgen Schulz ,  Paul Loewenstein

    IPC: G06F12/08

    CPC classification number: G06F12/0833 ,  G06F12/0828 ,  G06F2212/621

    Abstract: A directory structure that may allow concurrent processing of write-back and clean victimization requests is disclosed. The directory structure may include a memory configured to store a plurality of entries, where each entry may include information indicative of a status of a respective entry in a cache memory. Update requests for the entries in the memory may be received and stored. A subset of previously stored update requests may be selected. Each update request of the subset of the previously stored update requests may then be processed concurrently.

    Abstract translation: 公开了可以允许并发处理回写和干净的受害请求的目录结构。 目录结构可以包括被配置为存储多个条目的存储器，其中每个条目可以包括指示高速缓冲存储器中相应条目的状态的信息。 可以接收并存储对存储器中的条目的更新请求。 可以选择先前存储的更新请求的子集。 然后可以同时处理先前存储的更新请求的子集的每个更新请求。

    OBSERVATION OF DATA IN PERSISTENT MEMORY
    2.
    发明申请
    OBSERVATION OF DATA IN PERSISTENT MEMORY 有权
    观察记忆中的数据

    公开(公告)号：US20140365734A1

    公开(公告)日：2014-12-11

    申请号：US13914001

    申请日：2013-06-10

    Applicant: Oracle International Corporation

    Inventor： William H. Bridge, JR. ,  Paul Loewenstein ,  Mark A. Luttrell

    IPC: G06F12/08

    CPC classification number: G06F12/0891 ,  G06F9/52 ,  G06F12/0804 ,  G06F12/0815 ,  G06F12/0831 ,  G06F12/0833 ,  G06F12/084 ,  G06F12/0868

    Abstract: Systems and methods for reliably using data storage media. Multiple processors are configured to access a persistent memory. For a given data block corresponding to a write access request from a first processor to the persistent memory, a cache controller prevents any read access of a copy of the given data block in an associated cache. The cache controller prevents any read access while detecting an acknowledgment that the given data block is stored in the persistent memory is not yet received. Until the acknowledgment is received, the cache controller allows write access of the copy of the given data block in the associated cache only for a thread in the first processor that originally sent the write access request. The cache controller invalidates any copy of the given data block in any cache levels below the associated cache.

    Abstract translation: 可靠地使用数据存储介质的系统和方法。 多个处理器被配置为访问持久存储器。 对于对应于从第一处理器到持久存储器的写访问请求的给定数据块，高速缓存控制器防止在相关联的高速缓存中的给定数据块的副本的任何读访问。 高速缓存控制器在检测到尚未接收到持久存储器中存储给定数据块的确认时防止任何读访问。 在接收到确认之前，高速缓存控制器允许仅对最初发送写访问请求的第一处理器中的线程对相关联的高速缓存中的给定数据块的副本进行写访问。 高速缓存控制器使相关高速缓存下的任何缓存级别的给定数据块的任何副本无效。

    INTER-PROCESSOR BUS LINK AND SWITCH CHIP FAILURE RECOVERY
    4.
    发明申请
    INTER-PROCESSOR BUS LINK AND SWITCH CHIP FAILURE RECOVERY 有权
    处理器总线链路和切换芯片故障恢复

    公开(公告)号：US20160210255A1

    公开(公告)日：2016-07-21

    申请号：US14598640

    申请日：2015-01-16

    Applicant: Oracle International Corporation

    Inventor： Thomas Wicki ,  David Smentek ,  Sumti Jairath ,  Kathirgamar Aingaran ,  Ali Vahidsafa ,  Paul Loewenstein

    IPC: G06F13/40 ,  G06F11/22 ,  G06F11/30

    CPC classification number: G06F13/4022 ,  G06F11/221 ,  H04L12/00 ,  H04L12/4625

    Abstract: A system is disclosed in which the system may include multiple bus switches, and multiple processors. Each processor may be coupled to each bus switch. Each processor may be configured to initiate a transfer of data to a given bus switch, and detect if a respective link to the given bus switch is inoperable. In response to detecting an inoperable link to a first bus switch, a given processor may be further configured to send a notification message to at least one other processor via at least a second bus switch and to remove routing information corresponding to the inoperable link from a first register. The at least one other processor may be configured to remove additional routing information corresponding to the inoperable link from a second register in response to receiving the notification message from the given processor.

    Abstract translation: 公开了一种系统，其中系统可以包括多个总线开关和多个处理器。 每个处理器可以耦合到每个总线开关。 每个处理器可以被配置为启动数据到给定总线开关的传输，并检测到给定总线开关的相应链路是否不可操作。 响应于检测到不可操作的链接到第一总线交换机，给定处理器可以进一步被配置为经由至少第二总线交换机向至少一个其他处理器发送通知消息，并且从一个第二总线交换机去除对应于不可操作链路的路由信息 首先注册 响应于从给定处理器接收到通知消息，至少一个其他处理器可以被配置为从第二寄存器去除对应于不可操作链路的附加路由信息。

    DIGITAL ENCODING OF PARALLEL BUSSES TO SUPPRESS SIMULTANEOUS SWITCHING OUTPUT NOISE
    5.
    发明申请
    DIGITAL ENCODING OF PARALLEL BUSSES TO SUPPRESS SIMULTANEOUS SWITCHING OUTPUT NOISE 有权
    数字编码并行总线同时抑制同时开关输出噪声

    公开(公告)号：US20160164539A1

    公开(公告)日：2016-06-09

    申请号：US14563485

    申请日：2014-12-08

    Applicant: Oracle International Corporation

    Inventor： Robert P. Masleid ,  Don Draper ,  Venkat Krishnaswamy ,  Paul Loewenstein

    IPC: H03M13/21 ,  G06F11/16

    CPC classification number: G06F11/1625 ,  G06F11/00 ,  H03M5/00 ,  H03M7/00 ,  H03M13/09

    Abstract: An apparatus and method for encoding data are disclosed that may allow for different encoding levels of transmitted data. The apparatus may include an encoder unit and a plurality of transceiver units. The encoder unit may be configured to receive a plurality of data words, where each data word includes N data bits, wherein N is a positive integer greater than one, and encode a first data word of the plurality of data words. The encoded first data word may include M data bits, where M is a positive integer greater than N. Each transceiver unit may transmit a respective data bit of the encoded first data word. The encoder unit may be further configured to receive information indicative of a quality of transmission of the encoded first data word, and encode a second data word of the plurality of data words dependent upon the quality.

    Abstract translation: 公开了一种用于编码数据的装置和方法，其可以允许发送数据的不同编码级别。 该装置可以包括编码器单元和多个收发器单元。 编码器单元可以被配置为接收多个数据字，其中每个数据字包括N个数据位，其中N是大于1的正整数，并且对多个数据字的第一数据字进行编码。 编码的第一数据字可以包括M个数据位，其中M是大于N的正整数。每个收发器单元可以发送编码的第一数据字的相应数据位。 编码器单元还可以被配置为接收指示编码的第一数据字的传输质量的信息，并且根据质量来编码多个数据字中的第二数据字。

    CODEC TO REDUCE SIMULTANEOUSLY SWITCHING OUTPUTS
    9.
    发明申请
    CODEC TO REDUCE SIMULTANEOUSLY SWITCHING OUTPUTS 有权
    编解码器减少同时切换输出

    公开(公告)号：US20150371693A1

    公开(公告)日：2015-12-24

    申请号：US14310269

    申请日：2014-06-20

    Applicant: Oracle International Corporation

    Inventor： Robert P. Masleid ,  Don Draper ,  Venkat Krishnaswamy ,  Paul Loewenstein

    IPC: G11C8/10 ,  G11C8/06

    CPC classification number: G11C8/10 ,  G06F11/1048 ,  G11C7/1006 ,  G11C8/06

    Abstract: Embodiments of an apparatus and method for encoding data are disclosed that may allow for reduced simultaneous switching output noise. The apparatus may include a row decode circuit, a column decode circuit, and a memory array. The row decode circuit and column decode circuits may be configured to decode a first portion and a second portion, respectively, of a given data word of a first plurality of data words, where each data word may include N data bits, and where N is an integer greater than one. The memory array may be configured to store a second plurality of data words where each data word may include M data bits, and where M is an integer greater than N. The memory array may be further configured to retrieve a given data word of the second plurality of data words dependent upon the decoded first and second portions.

    Abstract translation: 公开了一种用于编码数据的装置和方法的实施例，其可以允许降低的同时开关输出噪声。 该装置可以包括行解码电路，列解码电路和存储器阵列。 行解码电路和列解码电路可以被配置为分别解码第一多个数据字的给定数据字的第一部分和第二部分，其中每个数据字可以包括N个数据位，并且其中N是 大于1的整数。 存储器阵列可以被配置为存储第二多个数据字，其中每个数据字可以包括M个数据位，并且其中M是大于N的整数。存储器阵列还可以被配置为检索第二个数据字的给定数据字 取决于解码的第一和第二部分的多个数据字。

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