利索-全球专利检索

  1. 登录
  2. 注册

搜索结果

18 条记录 (耗时 0.019 秒)

    Performance Analysis Based System Level Power Management
    3.
    发明申请
    Performance Analysis Based System Level Power Management 审中-公开
    基于性能分析的系统级电源管理

    公开(公告)号：US20080301474A1

    公开(公告)日：2008-12-04

    申请号：US12158996

    申请日：2006-12-21

    申请人： Nagaraju Bussa ,  Harsh Dhand ,  Balakrishnan Srinivasan

    发明人： Nagaraju Bussa ,  Harsh Dhand ,  Balakrishnan Srinivasan

    IPC分类号： G06F1/32

    CPC分类号： G06F1/3203 ,  G06F1/3296 ,  Y02D10/172

    摘要： A multiprocessor system-on-chip 102 with dynamic adaptive power management for execution of data-dependent applications comprises strategically placed performance counters to collect run-time performance requirements of tasks. A power manager 130 issues DVS 132, DFS 134, time-out 136, and other controls to the various system resources being monitored. As the tasks execute during run-time, the quality of the match between the task and the resource it was scheduled to is analyzed. More accurate power controls and schedules are then made available and stored in a performance requirements table. The power-management is therefore adaptive and dynamic. During a static analysis phase, applications and tasks that can be pre-characterized for their performance requirements are profiled and pre-loaded as initial starting points for correction during run-time.

    摘要翻译： 具有用于执行数据相关应用的动态自适应功率管理的多处理器片上系统102包括用于收集任务的运行时性能要求的策略性放置的性能计数器。 电源管理器130向被监视的各种系统资源发出DVS 132，DFS 134，超时136和其他控制。 随着任务在运行时执行，分析了任务与计划的资源之间的匹配质量。 然后，更精确的电源控制和计划可用并存储在性能要求表中。 因此，电力管理是适应性和动态的。 在静态分析阶段，可以对其性能要求进行预先表征的应用程序和任务进行轮廓化和预加载，作为运行时更正的初始起点。

    Data processing apparatus with parallel operating functional units
    4.
    发明申请
    Data processing apparatus with parallel operating functional units 有权
    具有并行运行功能单元的数据处理装置

    公开(公告)号：US20050273569A1

    公开(公告)日：2005-12-08

    申请号：US10530375

    申请日：2003-09-17

    申请人： Carlos Alba Pinto ,  Ramanathan Sethuraman ,  Balakrishnan Srinivasan ,  harm Johannes Peters ,  Rafael Peset Llopis

    发明人： Carlos Alba Pinto ,  Ramanathan Sethuraman ,  Balakrishnan Srinivasan ,  harm Johannes Peters ,  Rafael Peset Llopis

    IPC分类号： G06F9/30 ,  G06F9/32 ,  G06F9/38 ,  G06F12/00

    CPC分类号： G06F9/3802 ,  G06F9/3853

    摘要： A program of instruction words is executed with a VLIW data processing apparatus. The apparatus comprises a plurality of functional units capable of executing a plurality of instructions from each instruction word in parallel. The instructions from each of at least some of the instruction words are fetched from respective memory units in parallel, addressed with an instruction address that is common for the functional units. Translation of the instruction address into a physical address can be modified for one or more particular ones of the memory units. Modification is controlled by modification update instructions in the program. Thus, it can be selected dependent on program execution which instructions from the memory units will be combined into the instruction word in response to the instruction address.

    摘要翻译： 用VLIW数据处理装置执行指令字的程序。 该装置包括能够并行地从每个指令字执行多个指令的多个功能单元。 来自各个指令字中的至少一些的指令被并行地从相应的存储器单元中取出，用功能单元共用的指令地址寻址。 将指令地址转换为物理地址可以针对一个或多个特定存储器单元进行修改。 修改由程序中的修改更新指令控制。 因此，可以根据程序执行来选择来自存储器单元的指令将响应于指令地址而组合到指令字中。

    Pipelined instruction processor with data bypassing and disabling circuit
    5.
    发明授权
    Pipelined instruction processor with data bypassing and disabling circuit 有权
    带数据旁路和禁用电路的流水线指令处理器

    公开(公告)号：US07730284B2

    公开(公告)日：2010-06-01

    申请号：US10549368

    申请日：2004-03-17

    申请人： Balakrishnan Srinivasan ,  Ramanathan Sethuraman ,  Carlos Antonio Alba Pinto

    发明人： Balakrishnan Srinivasan ,  Ramanathan Sethuraman ,  Carlos Antonio Alba Pinto

    IPC分类号： G06F9/30

    CPC分类号： G06F8/445 ,  G06F9/30141 ,  G06F9/3826 ,  G06F9/3859 ,  G06F9/3865 ,  G06F9/3869

    摘要： An instruction processing device has a of pipe-line stage with a functional unit for executing a command from an instruction. A first register unit is coupled to the functional unit for storing a result of execution of the command when the command has reached a first one of the pipeline stages, and for supplying bypass operand data to the functional unit. A register file is coupled to the functional unit for storing the result when the command has reached a second one of the pipeline stages, downstream from the first one of the pipeline stages, and for supplying operand data to the functional unit. A disable circuit is coupled to selectively disable storing of the results in the register file under control of the instructions.

    摘要翻译： 指令处理装置具有管线级，其具有用于从指令执行命令的功能单元。 第一寄存器单元耦合到功能单元，用于当命令已经到达第一个流水线级时存储命令的执行结果，并且用于将旁路操作数数据提供给功能单元。 寄存器文件耦合到功能单元，用于当命令已经到达第一个流水线级的第一个流水线级的下游，并且将操作数数据提供给功能单元时存储结果。 耦合禁止电路以在指令的控制下选择性地禁止将结果存储在寄存器文件中。

    Instruction Controlled Data Processing Device
    6.
    发明申请
    Instruction Controlled Data Processing Device 有权
    指令控制数据处理装置

    公开(公告)号：US20080133880A1

    公开(公告)日：2008-06-05

    申请号：US10561454

    申请日：2004-06-22

    申请人： Carlos Antonio Alba Pinto ,  Balakrishnan Srinivasan ,  Ramanathan Sethuraman

    发明人： Carlos Antonio Alba Pinto ,  Balakrishnan Srinivasan ,  Ramanathan Sethuraman

    IPC分类号： G06F15/76 ,  G06F9/30

    CPC分类号： G06F9/3826 ,  G06F1/3203 ,  G06F1/324 ,  G06F1/3243 ,  G06F9/3824 ,  G06F9/3836 ,  G06F9/3853 ,  G06F9/3869 ,  G06F9/3885 ,  Y02D10/126 ,  Y02D10/152

    摘要： The data processing device has a plurality of functional units and issues instructions in successive instruction cycles. Instructions of a first type are each intended for one functional unit at a time. An instruction of a second type causes a combination of functional units to respond in the same instruction execution cycle, a result from one functional unit being used by another as part of the execution of the same instruction. Preferably, the device supports alternative operation at a number of different instruction cycle rates, dependent on whether an executed program segment contains instructions of the second type. The fastest instruction cycle rate does not allow execution of the instruction of the second type, because operation by different functional units does not fit within the instruction execution cycle. When possible, the device saves power by switching to a slower clock rate, in which case instructions of the second type are executed to save additional power, by reducing the number of instructions that have to be issued.

    摘要翻译： 数据处理装置具有多个功能单元并在连续的指令周期中发出指令。 第一种类型的说明每次都用于一个功能单元。 第二类型的指令使得功能单元的组合在相同的指令执行周期中作出响应，这是由另一个功能单元作为执行相同指令的一部分使用的结果。 优选地，该设备支持多个不同指令周期速率的替代操作，取决于所执行的程序段是否包含第二类型的指令。 最快的指令周期速率不允许执行第二种指令，因为不同功能单元的操作不符合指令执行周期。 如果可能，设备通过切换到较慢的时钟速率来节省功率，在这种情况下，通过减少必须发出的指令数量来执行第二种类型的指令以节省额外的功率。

    MEMS based tunable antenna for wireless reception and transmission
    7.
    发明授权
    MEMS based tunable antenna for wireless reception and transmission 有权
    基于MEMS的可调谐天线，用于无线接收和传输

    公开(公告)号：US07167135B2

    公开(公告)日：2007-01-23

    申请号：US10877456

    申请日：2004-06-25

    申请人： Issy Kipnis ,  Valluri Rao ,  Balakrishnan Srinivasan ,  Joe Hayden, III

    发明人： Issy Kipnis ,  Valluri Rao ,  Balakrishnan Srinivasan ,  Joe Hayden, III

    IPC分类号： H01Q9/00

    CPC分类号： H01Q9/0442 ,  H01Q1/38 ,  H01Q9/0407

    摘要： An antenna for a wireless device may be kept dynamically tuned to a desired center frequency to compensate for detuning which may be caused by environmental influences. A sensor provides a feedback signal to a controller to select an appropriate capacitance value from a variable capacitor to tune the antenna for the wireless device. The variable capacitor may comprise a plurality of fixed capacitors and MEMS switches arranged in parallel or may comprise a variable MEMS capacitor having a fixed lower plate and a flexible upper plate.

    摘要翻译： 可以将用于无线设备的天线保持动态地调谐到期望的中心频率以补偿可能由环境影响引起的失谐。 传感器向控制器提供反馈信号以从可变电容器选择适当的电容值，以调谐无线设备的天线。 可变电容器可以包括并联布置的多个固定电容器和MEMS开关，或者可以包括具有固定下板和柔性上板的可变MEMS电容器。

    Pipelined instruction processor with data bypassing
    8.
    发明申请
    Pipelined instruction processor with data bypassing 有权
    流水线指令处理器，数据旁路

    公开(公告)号：US20060212686A1

    公开(公告)日：2006-09-21

    申请号：US10549368

    申请日：2004-03-17

    申请人： Balakrishnan Srinivasan ,  Ramanathan Sethuraman ,  Carlos Alba Pinto

    发明人： Balakrishnan Srinivasan ,  Ramanathan Sethuraman ,  Carlos Alba Pinto

    IPC分类号： G06F9/44

    CPC分类号： G06F8/445 ,  G06F9/30141 ,  G06F9/3826 ,  G06F9/3859 ,  G06F9/3865 ,  G06F9/3869

    摘要： An instruction processing device has a of pipe-line stage with a functional unit for executing a command from an instruction. A first register unit is coupled to the functional unit for storing a result of execution of the command when the command has reached a first one of the pipeline stages, and for supplying bypass operand data to the functional unit. A register file is coupled to the functional unit for storing the result when the command has reached a second one of the pipeline stages, downstream from the first one of the pipeline stages, and for supplying operand data to the functional unit. A disable circuit is coupled to control of the instructions.

    摘要翻译： 指令处理装置具有管线级，其具有用于从指令执行命令的功能单元。 第一寄存器单元耦合到功能单元，用于当命令已经到达第一个流水线级时存储命令的执行结果，并且用于将旁路操作数数据提供给功能单元。 寄存器文件耦合到功能单元，用于当命令已经到达第一个流水线级的第一个流水线级的下游，并且将操作数数据提供给功能单元时存储结果。 禁用电路耦合到控制指令。

    DATA PROCESSING APPARATUS ADDRESS RANGE DEPENDENT PARALLELIZATION OF INSTRUCTIONS
    10.
    发明申请
    DATA PROCESSING APPARATUS ADDRESS RANGE DEPENDENT PARALLELIZATION OF INSTRUCTIONS 审中-公开
    数据处理设备地址范围依赖于指令的并行

    公开(公告)号：US20130138927A1

    公开(公告)日：2013-05-30

    申请号：US13751324

    申请日：2013-01-28

    申请人： Ramanathan Sethuraman ,  Balakrishnan Srinivasan ,  Carlos Alba Pinto ,  Harm Peters ,  Rafael Peset LLopis

    发明人： Ramanathan Sethuraman ,  Balakrishnan Srinivasan ,  Carlos Alba Pinto ,  Harm Peters ,  Rafael Peset LLopis

    IPC分类号： G06F9/30

    CPC分类号： G06F9/30003 ,  G06F9/30149 ,  G06F9/3802 ,  G06F9/3853

    摘要： A data processing apparatus has an instruction memory system arranged to output an instruction word addressed by an instruction address. An instruction execution unit, processes a plurality of instructions from the instruction word in parallel. A detection unit, detects in which of a plurality of ranges the instruction address lies. The detection unit is coupled to the instruction execution unit and/or the instruction memory system, to control a way in which the instruction execution unit parallelizes processing of the instructions from the instruction word, dependent on a detected range. In an embodiment the instruction execution unit and/or the instruction memory system adjusts a width of the instruction word that determines a number of instructions from the instruction word that is processed in parallel, dependent on the detected range.

    摘要翻译： 数据处理装置具有布置成输出由指令地址寻址的指令字的指令存储器系统。 指令执行单元，并行地从指令字处理多个指令。 检测单元，检测指示地址所在的多个范围中的哪一个。 检测单元耦合到指令执行单元和/或指令存储器系统，以根据检测到的范围来控制指令执行单元将来自指令字的指令的处理并行化的方式。 在一个实施例中，指令执行单元和/或指令存储器系统根据检测到的范围来调整从并行处理的指令字确定指令字数的指令字的宽度。