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    Fully differential ESD circuit for high-frequency applications
    1.
    发明授权
    Fully differential ESD circuit for high-frequency applications 有权

    公开(公告)号：US12244138B2

    公开(公告)日：2025-03-04

    申请号：US18070386

    申请日：2022-11-28

    Applicant: QUALCOMM Incorporated

    Inventor： Kshitij Yadav ,  Vijayakumar Dhanasekaran ,  Khaled Mahmoud Abdelfattah Aly ,  Ramkumar Sivakumar

    IPC: H02H9/04

    Abstract: A differential ESD circuit is provided for protecting a pair of differential terminals of an integrated circuit from electrostatic shock. A first diode couples between a first terminal in the pair of differential terminals and a first resistor that couples to a voltage node of the integrated circuit. Similarly, a second diode couples between a second terminal in the pair of differential terminals and a second resistor that couples to the voltage node of the integrated circuit. The first and second resistors isolate the first and second terminals from a capacitive loading that would otherwise exist from the first and second diodes.

    Sampling network and clocking scheme for a switched-capacitor integrator
    3.
    发明授权
    Sampling network and clocking scheme for a switched-capacitor integrator 有权
    开关电容积分器的采样网络和时钟方案

    公开(公告)号：US09558845B2

    公开(公告)日：2017-01-31

    申请号：US14700696

    申请日：2015-04-30

    Applicant: QUALCOMM Incorporated

    Inventor： Wenchang Huang ,  Ramkumar Sivakumar

    IPC: G06F7/64 ,  G06G7/18 ,  G06G7/19 ,  G11C27/02 ,  H03H19/00

    CPC classification number: G11C27/026 ,  H03H19/004 ,  H03M3/342

    Abstract: Certain aspects of the present disclosure generally relate to a sampling network of a switched-capacitor integrator and a clocking scheme associated therewith, which may be used in an analog-to-digital converter (ADC), for example. The integrator generally includes five sets of switches which allow for a decreased switching frequency (e.g., halved) at an input stage of the integrator compared to conventional double sampling networks. As a result, the input impedance of the integrator may be increased (e.g., doubled), resulting in lower power consumption and reduced strain on driving circuitry.

    Abstract translation: 本公开的某些方面通常涉及开关电容积分器的采样网络和与其相关联的时钟方案，其可以例如在模数转换器（ADC）中使用。 积分器通常包括五组开关，其允许与常规双采样网络相比在积分器的输入级降低开关频率（例如，减半）。 结果，积分器的输入阻抗可以增加（例如，加倍），导致较低的功率消耗和减小的驱动电路的应变。

    Area efficient level translating trigger circuit for electrostatic discharge events
    4.
    发明授权
    Area efficient level translating trigger circuit for electrostatic discharge events 有权

    公开(公告)号：US11799287B2

    公开(公告)日：2023-10-24

    申请号：US17522729

    申请日：2021-11-09

    Applicant: QUALCOMM Incorporated

    Inventor： Ramkumar Sivakumar ,  Subbarao Surendra Chakkirala

    IPC: H02H9/04 ,  H02H1/00

    CPC classification number: H02H9/046 ,  H02H1/0007

    Abstract: A trigger circuit includes a first capacitor and a second capacitor connected in series, a control device and an output of the trigger circuit. The first capacitor is connected to a first voltage rail and to a common node. The second capacitor is connected to a second voltage rail and to the common node. The control device has a first terminal that is coupled to the common node and a control terminal to receive a control signal. The control signal may be decoupled from transients on the first voltage rail and the second voltage rail. The output of the trigger circuit is coupled to the common node.

    Voltage-to-current architecture and error correction schemes
    5.
    发明授权
    Voltage-to-current architecture and error correction schemes 有权

    公开(公告)号：US11536749B2

    公开(公告)日：2022-12-27

    申请号：US17154758

    申请日：2021-01-21

    Applicant: QUALCOMM Incorporated

    Inventor： Ramkumar Sivakumar ,  Jingxue Lu ,  Sherif Galal ,  Xinwang Zhang ,  Kshitij Yadav

    IPC: H03F3/20 ,  H03F1/00 ,  H04R3/00 ,  G01R19/00 ,  H03F3/217 ,  H03F1/02

    Abstract: Certain aspects of the present disclosure are generally directed to circuitry and techniques for voltage-to-current conversion. For example, certain aspects provide a circuit for signal amplification including a first amplifier; a first transistor, a gate of the first transistor being coupled to an output of the first amplifier and a drain of the first transistor being coupled to an output node of circuit; a first resistive element coupled between a first input node of the circuit and an input of the first amplifier; a second amplifier; a second transistor, a gate of the second transistor being coupled to an output of the second amplifier and a drain of the second transistor being coupled to the output node of circuit; and a second resistive element coupled between a second input node of the circuit and an input of the second amplifier.

    CIRCUITS FOR SEMICONDUCTOR DEVICE LEAKAGE CANCELLATION
    6.
    发明申请
    CIRCUITS FOR SEMICONDUCTOR DEVICE LEAKAGE CANCELLATION 审中-公开
    用于半导体器件泄漏电路的电路

    公开(公告)号：US20150002209A1

    公开(公告)日：2015-01-01

    申请号：US13930792

    申请日：2013-06-28

    Applicant: QUALCOMM INCORPORATED

    Inventor： Ramkumar Sivakumar

    IPC: H03K17/687

    CPC classification number: H03K17/687 ,  G11C7/12 ,  H03F3/45968 ,  H03F2203/45514 ,  H03F2203/45586 ,  H03F2203/45588

    Abstract: One feature pertains to a circuit comprising a semiconductor leakage source device and a semiconductor leakage cancellation device that are both coupled to a signal line. The leakage source device generates a leakage current on the signal line, and the leakage cancellation device generates a leakage cancellation current on the signal line. The leakage cancellation device is sized and shaped in relation to the leakage source device such that the leakage cancellation current effectively cancels the leakage current on the signal line. Moreover, the leakage cancellation current cancels the leakage current on the signal line despite variations in at least one of process, temperature, and/or signal line voltages. In one example, the signal line is a virtual ground node of a capacitive feedback amplifier and the leakage source device is a switch between the virtual ground node and a first terminal of a feedback capacitor of the amplifier.

    Abstract translation: 一个特征涉及包括耦合到信号线的半导体泄漏源装置和半导体泄漏消除装置的电路。 泄漏源装置在信号线上产生泄漏电流，泄漏消除装置在信号线上产生泄漏消除电流。 泄漏消除装置的尺寸和形状相对于泄漏源装置成形，使得泄漏抵消电流有效地消除信号线上的泄漏电流。 此外，尽管在工艺，温度和/或信号线电压中的至少一个有变化，但是泄漏抵消电流消除了信号线上的漏电流。 在一个示例中，信号线是电容性反馈放大器的虚拟接地节点，并且泄漏源装置是虚拟接地节点与放大器的反馈电容器的第一端子之间的开关。

    INTEGRATED TRANSIENT VOLTAGE SUPPRESSOR CIRCUIT
    9.
    发明申请
    INTEGRATED TRANSIENT VOLTAGE SUPPRESSOR CIRCUIT 审中-公开

    公开(公告)号：US20180374705A1

    公开(公告)日：2018-12-27

    申请号：US15632040

    申请日：2017-06-23

    Applicant: QUALCOMM Incorporated

    Inventor： Vijayakumar Dhanasekaran ,  Ramkumar Sivakumar ,  Arash Mehrabi

    IPC: H01L21/265 ,  H01L27/08 ,  H01L29/93 ,  H01L29/861 ,  H01L27/02 ,  H01L29/87 ,  H01L29/06

    Abstract: A transient signal protection circuit includes an input node coupled to a signal line configured to carry an output signal from a first circuit to a second circuit, wherein the signal line is subject to experiencing an unwanted reverse signal from the second circuit to the first circuit. The transient signal protection circuit also includes a comparator module configured to output a clamping signal when it is determined that the unwanted reverse signal includes a value that falls outside an acceptable range of the first circuit; and a power switch coupled to the comparator module and configured to couple the input node to a sink node when the comparator module outputs the clamping signal.

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