公开(公告)号：US20160313977A1

公开(公告)日：2016-10-27

申请号：US14692071

申请日：2015-04-21

Applicant: QUALCOMM Incorporated

Inventor： Kenneth Alan DOCKSER ,  Michael Thomas DIBRINO ,  Pathik Sunil LALL

IPC: G06F7/535 ,  G06F5/01

CPC classification number: G06F7/535 ,  G06F5/01 ,  G06F7/4873 ,  G06F7/5375 ,  G06F2205/003 ,  G06F2207/535

Abstract: Systems and methods relate to division of a dividend by a divisor, with fast result formatting. Counts of leading sign bits of the dividend and the divisor are determined. The dividend and the divisor are normalized based on their respective counts of leading sign bits to obtain a normalized dividend and a normalized divisor, respectively. An exact number of significant quotient bits of a quotient of the division, based on the normalized dividend, the normalized divisor, and the counts of leading sign bits of the dividend and the divisor and used to determine a correct position of a leading bit of the quotient based on this exact number. The quotient is developed by placing the leading bit at or near the correct position and appending less significant bits to the right of the leading bit. Thus, left-shifts in each iteration and large final shifts are avoided in formatting the result.

Abstract translation: 系统和方法涉及除数的分红，并具有快速的结果格式。 确定股息和除数的前导符号位数。 除数和除数根据它们各自的前导符号位的数量进行归一化，以分别获得归一化的除数和归一化除数。 基于归一化的除数，归一化除数和除数的前导符号位的计数，并且用于确定所述除法的前导位的正确位置的除法的商的显着商位的精确数量 基于这个确切数字的商。 通过将引导位置于或接近正确位置并将较低有效位附加到引导位的右侧来开发商。 因此，在格式化结果时避免了每次迭代中的左移和大的最终偏移。

公开(公告)号：US20160313976A1

公开(公告)日：2016-10-27

申请号：US14691576

申请日：2015-04-21

Applicant: QUALCOMM Incorporated

Inventor： Michael Thomas DIBRINO ,  Kenneth Alan DOCKSER ,  Pathik Sunil LALL

IPC: G06F7/52 ,  G06F7/537

CPC classification number: G06F7/52 ,  G06F7/537 ,  G06F7/5375 ,  G06F7/5525 ,  G06F2207/5528

Abstract: Systems and methods relate to a division/root computation unit. A lookup table according to a Sweeney, Robertson, and Tocher (SRT) algorithm for a division/root computation is stored in a memory. Information related to a selected column corresponding to a divisor/root estimate is stored in a high-speed memory. Division/root computation is performed iteratively using the cached information to improve access times and reduce latency of accessing the entire lookup table on each iteration. In each iteration, a quotient/root is determined from the cached information based on a current partial remainder, and a next partial remainder is generated based on the quotient/root, the divisor/root estimate, and the current partial remainder.

Abstract translation: 系统和方法涉及分区/根计算单元。 根据用于划分/根计算的Sweeney，Robertson和Tocher（SRT）算法的查找表存储在存储器中。 与对应于除数/根估计的所选列相关的信息被存储在高速存储器中。 使用缓存信息迭代地执行分区/根计算，以改善访问时间并减少在每次迭代时访问整个查找表的延迟。 在每次迭代中，根据当前部分余数从高速缓存的信息确定商/根，并且基于商/根，除数/根估计和当前部分余数来生成下一部分余数。

公开(公告)号：US20150019843A1

公开(公告)日：2015-01-15

申请号：US14091340

申请日：2013-11-27

Applicant: QUALCOMM Incorporated

Inventor： Anil KRISHNA ,  Sandeep S. NAVADA ,  Niket K. CHOUDHARY ,  Michael Scott MCILVAINE ,  Thomas Andrew SARTORIUS ,  Rodney Wayne SMITH ,  Kenneth Alan DOCKSER

IPC: G06F9/38

CPC classification number: G06F9/384 ,  G06F9/3824 ,  G06F9/3842 ,  G06F9/3855 ,  G06F9/3861

Abstract: A method and apparatus for allowing an out-of-order processor to reuse an in-use physical register is disclosed herein. The method and apparatus uses identifiers, such as tokens and/or other identifiers in a rename map table (RMT) and a physical register file (PRF), to indicate whether an instruction result is allowed or disallowed to be written into a physical register.

Abstract translation: 本文公开了一种允许无序处理器重用使用中物理寄存器的方法和装置。 该方法和装置使用诸如重命名映射表（RMT）和物理寄存器文件（PRF）中的令牌和/或其他标识符的标识符来指示是否允许或不允许将指令结果写入物理寄存器。

公开(公告)号：US20170255569A1

公开(公告)日：2017-09-07

申请号：US15057121

申请日：2016-03-01

Applicant: QUALCOMM Incorporated

Inventor： Thomas Andrew SARTORIUS ,  James Norris DIEFFENDERFER ,  Michael William MORROW ,  Jeffrey Todd BRIDGES ,  Michael Scott MCILVAINE ,  Rodney Wayne SMITH ,  Kenneth Alan DOCKSER ,  Thomas Philip SPEIER

IPC: G06F12/12 ,  G06F12/08 ,  G06F12/10

CPC classification number: G06F12/123 ,  G06F12/0811 ,  G06F12/0831 ,  G06F12/0871 ,  G06F12/0888 ,  G06F12/0891 ,  G06F12/0895 ,  G06F12/0897 ,  G06F12/1009 ,  G06F12/1027 ,  G06F12/12 ,  G06F12/126 ,  G06F2212/604 ,  G06F2212/6046 ,  G06F2212/621 ,  G06F2212/684

Abstract: Systems and methods for managing access to a cache relate to determining one or more execute permissions associated with a write-address of a write-request to the cache. The cache may be a unified cache for storing data as well as instructions. If there is a write-miss in the cache for the write-request, a cache controller may determine whether to implement a write-allocate policy or a write-no-allocate policy for servicing the write-miss, based on the one or more execute permissions. The one or more execute permissions can relate to a privilege level associated with the write-address. Execute permissions of a producing agent which generated the write-request and an execute permission of a consuming agent which can execute from the write-address may be based on the privilege levels of the producing agent and the consuming agent, respectively.

公开(公告)号：US20160342530A1

公开(公告)日：2016-11-24

申请号：US14716947

申请日：2015-05-20

Applicant: QUALCOMM Incorporated

Inventor： Henry Arthur PELLERIN, III ,  Thomas Philip SPEIER ,  Thomas Andrew SARTORIUS ,  Michael William MORROW ,  James Norris DIEFFENDERFER ,  Kenneth Alan DOCKSER ,  Michael Scott MCILVAINE

IPC: G06F12/12 ,  G06F12/08

CPC classification number: G06F12/128 ,  G06F12/0855 ,  G06F12/0864 ,  G06F12/0875 ,  G06F12/0895 ,  G06F2212/1016 ,  G06F2212/401 ,  G06F2212/6032 ,  G06F2212/621

Abstract: A memory structure compresses a portion of a memory tag using an indexed tag compression structure. A set of higher order bits of the memory tag may be stored in the indexed tag compression structure, where the set of higher order bits are identified by an index value. A tag array stores a set of lower order bits of the memory tag and the index value identifying the entry in the tag compression structure storing the set of higher order bits of the memory tag. The memory tag may comprise at least a portion of a memory address of a data element stored in a data array.

Abstract translation: 存储器结构使用索引标签压缩结构压缩存储器标签的一部分。 存储器标签的一组较高位可以存储在索引标签压缩结构中，其中较高位的集合由索引值标识。 标签阵列存储存储器标签的一组较低位，以及标识在存储标签的较高位的集合的标签压缩结构中的条目的索引值。 存储器标签可以包括存储在数据阵列中的数据元素的存储器地址的至少一部分。