公开(公告)号：US11749332B2

公开(公告)日：2023-09-05

申请号：US17174073

申请日：2021-02-11

Applicant: QUALCOMM Incorporated

Inventor： Kunal Desai ,  Saurabh Jaiswal ,  Vikrant Kumar ,  Swaraj Sha ,  Dharmesh Parikh

IPC: G11C29/00 ,  G11C11/406 ,  G06F12/06 ,  G11C11/408 ,  G11C11/4093

CPC classification number: G11C11/40618 ,  G06F12/0607 ,  G11C11/408 ,  G11C11/4093 ,  G11C11/40615 ,  G06F12/06

Abstract: Various embodiments include methods and devices for portion interleaving for asymmetric size memory portions. Embodiments may include determining an asymmetric memory portion assignment for an interleave unit, determining a consumed address space offset for consumed address space of a memory, modifying an address of the interleave unit using the consumed address space offset, and assigning the interleave unit to an interleave granule in the asymmetric memory portion using the modified address in a compact manner before assigning another interleave unit to another interleave granule. Embodiments may include receiving an address of memory access request in a memory, mapping the address to an interleave granule in an asymmetric memory portion, assigning consecutive interleave units to the interleave granule while the interleave granule has unused space before assigning another interleave unit to another interleave granule, and implementing the memory access request at the mapped address.

公开(公告)号：US20180373652A1

公开(公告)日：2018-12-27

申请号：US15634701

申请日：2017-06-27

Applicant: QUALCOMM INCORPORATED

Inventor： Vasantha Kumar Bandur Puttappa ,  Umesh Rao ,  Kunal Desai

IPC: G06F13/16 ,  H04B1/3827 ,  G06F15/78 ,  G06F11/30

Abstract: Methods and systems for dynamically controlling buffer size in a computing device in a computing device (“PCD”) are disclosed. A monitor module determines a first use case for defining a first activity level for a plurality of components of the PCD. Based on the first use case, a plurality of buffers are set to a fist buffer size. Each of the buffers is associated with one of the plurality of components, and the first buffer size for each buffer is based on the first activity level of the associated component. A second use case for the PCD, different from the first use case, is determined. The second use case defines a second activity level for the plurality of components. At least one of the buffers is set to a second buffer size different from the first buffer size based on the second use case.

公开(公告)号：US12298903B2

公开(公告)日：2025-05-13

申请号：US18314167

申请日：2023-05-09

Applicant: QUALCOMM Incorporated

Inventor： Kunal Desai ,  Saurabh Jaiswal ,  Vikrant Kumar ,  Swaraj Sha ,  Dharmesh Parikh

IPC: G06F12/06 ,  G11C11/406

Abstract: Various embodiments include methods and devices for portion interleaving for asymmetric size memory portions. Embodiments may include determining an asymmetric memory portion assignment for an interleave unit, determining a consumed address space offset for consumed address space of a memory, modifying an address of the interleave unit using the consumed address space offset, and assigning the interleave unit to an interleave granule in the asymmetric memory portion using the modified address in a compact manner before assigning another interleave unit to another interleave granule. Embodiments may include receiving an address of memory access request in a memory, mapping the address to an interleave granule in an asymmetric memory portion, assigning consecutive interleave units to the interleave granule while the interleave granule has unused space before assigning another interleave unit to another interleave granule, and implementing the memory access request at the mapped address.

公开(公告)号：US11809220B1

公开(公告)日：2023-11-07

申请号：US17725170

申请日：2022-04-20

Applicant: QUALCOMM INCORPORATED

Inventor： Deepak Kumar Agarwal ,  Kunal Desai ,  Jimit Shah ,  Rakesh Gehalot

IPC: G06F11/10

CPC classification number: G06F11/1044

Abstract: Error detection and correction (EDAC) logic of a memory subsystem may be monitored for error corrections, with the EDAC logic configured to use a first EDAC level. The number of error corrections made by the EDAC logic while using the first EDAC level during a time interval may be determined. The EDAC logic may be switched from using the first EDAC level to using a second EDAC level when the number of error corrections using the first EDAC level during the time interval exceeds a threshold.

公开(公告)号：US10713189B2

公开(公告)日：2020-07-14

申请号：US15634701

申请日：2017-06-27

Applicant: QUALCOMM INCORPORATED

Inventor： Vasantha Kumar Bandur Puttappa ,  Umesh Rao ,  Kunal Desai

IPC: G06F11/30 ,  G06F13/16 ,  H04B1/3827 ,  G06F15/78 ,  G06F5/06 ,  G06F1/32

Abstract: Methods and systems for dynamically controlling buffer size in a computing device in a computing device (“PCD”) are disclosed. A monitor module determines a first use case for defining a first activity level for a plurality of components of the PCD. Based on the first use case, a plurality of buffers are set to a first buffer size. Each of the buffers is associated with one of the plurality of components, and the first buffer size for each buffer is based on the first activity level of the associated component. A second use case for the PCD, different from the first use case, is determined. The second use case defines a second activity level for the plurality of components. At least one of the buffers is set to a second buffer size different from the first buffer size based on the second use case.

公开(公告)号：US12001288B2

公开(公告)日：2024-06-04

申请号：US17484310

申请日：2021-09-24

Applicant: QUALCOMM Incorporated

Inventor： Kunal Desai ,  Kiran Kumar Malipeddi ,  Shekar Babu Merla ,  Pranav Agrawal

IPC: G06F11/00 ,  G06F11/14 ,  G06F13/16 ,  G11C29/38

CPC classification number: G06F11/1428 ,  G06F11/1417 ,  G06F13/1668 ,  G11C29/38

Abstract: Various embodiments may include methods and systems for reconfiguring memory channel routing within a system-on-a-chip (SoC). A method may include obtaining first error information in response to misbehavior in a first memory channel communicatively connected to a network interface unit (NIU) of the SoC. The method may further include storing the first error information in non-volatile memory that is read upon booting of the SoC, and rebooting the SoC including the first memory channel. The method may further include configuring the first memory channel to be communicatively disconnected from the NIU and configuring a second memory channel to be communicatively connected to the NIU in response to reading the stored first error information during reboot.

公开(公告)号：US11640193B2

公开(公告)日：2023-05-02

申请号：US17485120

申请日：2021-09-24

Applicant: QUALCOMM INCORPORATED

Inventor： Kunal Desai ,  Ankit Shambhu ,  Srinivas Maddali ,  Sanjeev Shukla

IPC: G06F1/28 ,  G06F11/30 ,  G06F1/26 ,  G06F1/04 ,  G06F11/22 ,  G06F1/30

Abstract: A system-on-a-chip (“SoC”) in a computing device may be provided with a power delivery network (“PDN”) self-test to detect marginal PDN performance. In the self-test, a current surge may be generated on power supply connections of logic circuit blocks. Voltage monitors may measure voltage droop on the power supply connections responsive to the current surge. Voltage droop measurements may be compared with thresholds. An action, such as generation of an alert, may be performed if a voltage droop measurement exceeds a threshold.

公开(公告)号：US20230098902A1

公开(公告)日：2023-03-30

申请号：US17484310

申请日：2021-09-24

Applicant: QUALCOMM Incorporated

Inventor： Kunal Desai ,  Kiran Kumar Malipeddi ,  Shekar Babu Merla ,  Pranav Agrawal

IPC: G06F11/14 ,  G11C29/38 ,  G06F13/16

Abstract: Various embodiments may include methods and systems for reconfiguring memory channel routing within a system-on-a-chip (SoC). A method may include obtaining first error information in response to misbehavior in a first memory channel communicatively connected to a network interface unit (NIU) of the SoC. The method may further include storing the first error information in non-volatile memory that is read upon booting of the SoC, and rebooting the SoC including the first memory channel. The method may further include configuring the first memory channel to be communicatively disconnected from the NIU and configuring a second memory channel to be communicatively connected to the NIU in response to reading the stored first error information during reboot.

公开(公告)号：US10769073B2

公开(公告)日：2020-09-08

申请号：US15939031

申请日：2018-03-28

Applicant: QUALCOMM INCORPORATED

Inventor： Kunal Desai ,  Satyaki Mukherjee ,  Siddharth Kamdar ,  Abhinav Mittal ,  Vinayak Shrivastava

IPC: G06F12/10 ,  G06F3/06

Abstract: Systems, methods, and computer programs are disclosed for managing memory channel connectivity. One embodiment of a system comprises a high-bandwidth memory client, a low-bandwidth memory client, and an address translator. The high-bandwidth memory client is electrically coupled to each of a plurality of memory channels via an interconnect. The low-bandwidth memory client is electrically coupled to only a portion of the plurality of memory channels via the interconnect. The address translator is in communication with the high-bandwidth memory client and configured to perform physical address manipulation when a memory page to be accessed by the high-bandwidth memory client is shared with the low-bandwidth memory client.

公开(公告)号：US20170083461A1

公开(公告)日：2017-03-23

申请号：US14861114

申请日：2015-09-22

Applicant: QUALCOMM Incorporated

Inventor： Kunal Desai ,  Aniket Aphale ,  Umesh Rao

IPC: G06F13/16 ,  G06F13/40 ,  G06F3/06

CPC classification number: G06F13/1673 ,  G06F3/0611 ,  G06F3/0629 ,  G06F3/0673 ,  G06F13/1615 ,  G06F13/1689 ,  G06F13/4068

Abstract: An integrated circuit is provided with a memory controller coupled to a buffered command and address bus and a pipelined data bus having a pipeline delay. The memory controller is configured to control the write and read operations for an external memory having a write latency period requirement. The memory controller is further configured to launch write data into the pipelined data bus responsive to the expiration of a modified write latency period that is shorter than the write latency period.