公开(公告)号：US11733767B2

公开(公告)日：2023-08-22

申请号：US17359350

申请日：2021-06-25

Applicant: QUALCOMM Incorporated

Inventor： Prashanth Kumar Kakkireni ,  Matthew Severson ,  Kumar Kanti Ghosh ,  Shishir Joshi

IPC: G06F1/26 ,  G06F1/32 ,  G06F1/3296 ,  H04L12/10

CPC classification number: G06F1/3296 ,  H04L12/10

Abstract: Various embodiments may include methods and systems for power management of multiple chiplets within a system-on-a-chip (SoC). Various systems may include a power management integrated circuit (PMIC) configured to supply power to a first chiplet and a second chiplet across a shared power rail. The first chiplet may be configured to obtain first sensory information throughout the first chiplet. The second chiplet may be configured to obtain second sensory information throughout the second chiplet, and may be configured to transmit a voltage change message to the first chiplet based on the second sensory information. The first chiplet may be configured to transmit a power rail adjustment message to the PMIC based on the first sensory information and the voltage change message. The PMIC may be configured to adjust the voltage of at least one of the first chiplet and the second chiplet.

公开(公告)号：US11493970B2

公开(公告)日：2022-11-08

申请号：US17085505

申请日：2020-10-30

Applicant: QUALCOMM INCORPORATED

Inventor： Christopher Kong Yee Chun ,  Chandan Agarwalla ,  Dipti Ranjan Pal ,  Kumar Kanti Ghosh ,  Matthew Severson ,  Nilanjan Banerjee ,  Joshua Stubbs

IPC: G06F1/26 ,  G06F1/3296 ,  G06F1/3228 ,  G06F1/3287

Abstract: Dynamic power supply voltage adjustment in a computing device may involve two stages. In a first stage, a first method for adjusting a power supply voltage may be disabled. While the first method remains disabled, a request to adjust the power supply voltage from an initial value to a target value using a second method may be received. The second method may be initiated in response to the request if a time interval has elapsed since a previous request to adjust the power supply voltage. In a second stage, the first method may be enabled when it has been determined that the power supply voltage has reached the target value.

公开(公告)号：US20250103130A1

公开(公告)日：2025-03-27

申请号：US18475371

申请日：2023-09-27

Applicant: QUALCOMM Incorporated

Inventor： Mahadevamurty Nemani ,  Matthew Severson ,  Gabriel Watkins ,  Vijayakumar Ashok Dibbad ,  Ronald Alton ,  Lai Xu ,  Jeffrey Gemar

IPC: G06F1/3296 ,  G06F1/3206

Abstract: Power limiting in a processor-based system based on allocating power budgets for different sub-systems based on multiple time-based power limits is disclosed. The processor-based system has multiple power consuming sub-systems (e.g., non-processing unit (PU) and PU sub-systems) that demand and consume power from a power source of the processor-based system. To limit overall power consumption of the processor-based system over different time-based power limits, the processor-based system includes a power limiter circuit. The power limiter circuit is configured to manage multiple, different time-based (e.g., time constant) power limits for the processor-based system and to allocate corresponding power limit budgets to constrain power consumption of different sub-systems based on the multiple time-based power limits. The power limiter circuit can be configured to constrain power consumption of a PU sub-system to a total PU sub-system power limit budget based on the multiple time-based power limits.

公开(公告)号：US20230359373A1

公开(公告)日：2023-11-09

申请号：US17661810

申请日：2022-05-03

Applicant: QUALCOMM Incorporated

Inventor： Engin Ipek ,  Hamza Omar ,  Bohuslav Rychlik ,  Saumya Ranjan Kuanr ,  Behnam Dashtipour ,  Michael Hawjing Lo ,  Jeffrey Gemar ,  Matthew Severson ,  George Patsilaras ,  Andrew Edmund Turner

IPC: G06F3/06

CPC classification number: G06F3/0632 ,  G06F3/0604 ,  G06F3/0673

Abstract: Selective refresh techniques for memory devices are disclosed. In one aspect, a memory device that is used with an application that has frequent repeated read or write commands to certain memory segments may be able to set a flag or similar indication that exempts these certain memory segments from being actively refreshed. By exempting these memory segments from being actively refreshed, these memory segments are continuously available, thereby improving performance. Likewise, because these memory segments are so frequently the subject of a read or write command, these memory segments are indirectly refreshed through the execution of the read or write command.

公开(公告)号：US11625064B2

公开(公告)日：2023-04-11

申请号：US17402884

申请日：2021-08-16

Applicant: QUALCOMM Incorporated

Inventor： Naveen Kumar Narala ,  Matthew Severson ,  Haobo Zhao

IPC: G06F1/12 ,  G06F1/10 ,  G06F1/32 ,  G06F1/3206

Abstract: Various embodiments include methods and systems for providing sleep clock edge-based global counter synchronization in a multiple-chiplet system. A system-on-a-chip (SoC) may include a first chiplet including a first chiplet global counter subsystem, and a second chiplet including a second chiplet global counter subsystem. The SoC may further include an interface bus communicatively coupling the first chiplet and the second chiplet, and a power management integrated circuit (PMIC) configured to supply a sleep clock to the first chiplet and the second chiplet. The first chiplet may be configured to transmit a global counter synchronization pulse trigger to the second chiplet across the interface bus. The second chiplet may be configured to load a global counter synchronization value into the second chiplet global counter subsystem at a sleep clock synchronization edge of the sleep clock in response to receiving the global counter synchronization pulse trigger.

公开(公告)号：US20240264950A1

公开(公告)日：2024-08-08

申请号：US18163446

申请日：2023-02-02

Applicant: QUALCOMM Incorporated

Inventor： George Patsilaras ,  Engin Ipek ,  Goran Goran ,  Hamza Omar ,  Bohuslav Rychlik ,  Jeffrey Gemar ,  Matthew Severson ,  Andrew Edmund Turner

IPC: G06F12/126 ,  G06F12/0888

CPC classification number: G06F12/126 ,  G06F12/0888 ,  G06F2212/502

Abstract: Providing content-aware cache replacement and insertion policies in processor-based devices is disclosed. In some aspects, a processor-based device comprises a cache memory device and a cache controller circuit of the cache memory device. The cache controller circuit is configured to determine a plurality of content costs for each of a plurality of cached data values in the cache memory device, based on a plurality of bit values of each of the plurality of cached data values. The cache controller circuit is configured to identify, based on the plurality of content costs, a cached data value of the plurality of cached data values associated with a lowest content cost as a target cached data value. The cache controller circuit is also configured to evict the target cached data value from the cache memory device.

公开(公告)号：US11829172B2

公开(公告)日：2023-11-28

申请号：US17679811

申请日：2022-02-24

Applicant: QUALCOMM Incorporated

Inventor： Vijayakumar Ashok Dibbad ,  Fredrick Bontemps ,  Matthew Severson ,  Timothy Zoley

IPC: G05F1/62 ,  G05F1/56 ,  G01R19/165

CPC classification number: G05F1/56 ,  G01R19/16571 ,  G05F1/62

Abstract: An aspect of the disclosure relates to an apparatus including: an integrated circuit (IC) including one or more cores, and a current limit detection circuit; a voltage regulator; an inductor coupled between the voltage regulator and the one or more cores of the IC; and a current sensing circuit including inputs coupled across the inductor and an output coupled to the current limit detection circuit of the IC.

公开(公告)号：US11493980B1

公开(公告)日：2022-11-08

申请号：US17322402

申请日：2021-05-17

Applicant: QUALCOMM INCORPORATED

Inventor： Vijayakumar Ashok Dibbad ,  Bharat Kumar Rangarajan ,  Dipti Ranjan Pal ,  Keith Alan Bowman ,  Matthew Severson ,  Gordon Lee

IPC: G06F1/00 ,  G06F1/324 ,  H02H9/02 ,  G06F1/3296

Abstract: In controlling power in a portable computing device (“PCD”), a power supply input to a PCD subsystem may be modulated with a modulation signal when an over-current condition is detected. Detection of the modulation signal may indicate to a processing core of the subsystem to reduce its processing load. Compensation for the modulation signal in the power supply input may be applied so that the processing core is essentially unaffected by the modulation signal.

公开(公告)号：US12099397B2

公开(公告)日：2024-09-24

申请号：US18069537

申请日：2022-12-21

Applicant: QUALCOMM Incorporated

Inventor： Prashanth Kumar Kakkireni ,  Matthew Severson ,  Ravi Jenkal ,  Gordon Lee ,  Kevin Bradley Citterelle ,  Ronald Alton ,  Anish Muttreja

IPC: G06F1/32 ,  G06F1/3296

CPC classification number: G06F1/3296

Abstract: Various embodiments include power management system methods including receiving, at a processor(s), a notification signal triggering the processor(s) to implement power usage mitigation at the processor(s), determining, by the processor(s), a mitigation amount of power rail power by which to mitigate current usage at a power rail based on a use case for the power rail, and implementing power usage mitigation at the processor(s) by the processor(s) sufficient to mitigate power usage at the power rail by the mitigation amount of power rail power. Power usage mitigation may include reducing processor(s) current usage: by a predefined amount; proportional to the amount a power rail current exceeds a power rail current threshold; by the amount of current exceeding a processor current threshold; or by a smallest amount between the amount a power rail current exceeds a power rail current threshold and the processor(s) current exceeds a processor current threshold.

公开(公告)号：US11636057B2

公开(公告)日：2023-04-25

申请号：US17390215

申请日：2021-07-30

Applicant: QUALCOMM INCORPORATED

Inventor： Engin Ipek ,  Bohuslav Rychlik ,  George Patsilaras ,  Prajakt Kulkarni ,  Can Hankendi ,  Fahad Ali ,  Jeffrey Gemar ,  Matthew Severson

IPC: G06F13/16 ,  H03M5/14

Abstract: The energy consumed by data transfer in a computing device may be reduced by transferring data that has been encoded in a manner that reduces the number of one “1” data values, the number of signal level transitions, or both. A data destination component of the computing device may receive data encoded in such a manner from a data source component of the computing device over a data communication interconnect, such as an off-chip interconnect. The data may be encoded using minimum Hamming weight encoding, which reduces the number of one “1” data values. The received data may be decoded using minimum Hamming weight decoding. For other computing devices, the data may be encoded using maximum Hamming weight encoding, which increases the number of one “1” data values while reducing the number of zero “0” values, if reducing the number of zero values reduces energy consumption.