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公开(公告)号：US10199997B2
公开(公告)日：2019-02-05
申请号：US15178251
申请日：2016-06-09
Applicant: QUALCOMM Incorporated
Inventor： Rahul Karmaker
Abstract: Certain aspects of the present disclosure generally relate to using cross-coupled transistors for source degeneration of an amplification stage. For example, the amplification stage generally includes a differential amplifier comprising transistors, cross-coupled transistors coupled to the differential amplifier, and an impedance coupled between drains of the cross-coupled transistors. In certain aspects, the differential amplifier comprises a push-pull amplifier, and the transistors of the push-pull amplifier comprise cascode-connected transistors.
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公开(公告)号：US20180131356A1
公开(公告)日：2018-05-10
申请号：US15632238
申请日：2017-06-23
Applicant: QUALCOMM Incorporated
Inventor： Rahul Karmaker
Abstract: The present disclosure describes aspects of a fast settling peak detector. In some aspects, a peak detector circuit includes a first transistor having a gate coupled to an input of the circuit at which a signal is received and a drain coupled to a source of a second transistor. Current may flow in the first and second transistors responsive to the signal. The circuit also includes a third transistor having a gate coupled, via a signal-inverting component, to the input of the circuit and a drain coupled to a source of a fourth transistor. Through an inversion of the signal, other current flowing in the third and fourth transistor can reduce or cancel a frequency component of the current in the first and second transistors. In some cases, this precludes a need to filter the frequency component from an output of the circuit.
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公开(公告)号：US20160373062A1
公开(公告)日：2016-12-22
申请号：US14742351
申请日：2015-06-17
Applicant: QUALCOMM Incorporated
Inventor： Ayush Mittal , Gireesh Rajendran , Rahul Karmaker
CPC classification number: H03F1/0205 , H03F3/19 , H03F3/211 , H03F3/245 , H03F3/3022 , H03F3/45192 , H03F3/45219 , H03F3/45654 , H03F2200/294 , H03F2200/451 , H03F2203/21106 , H03F2203/30015 , H03F2203/45008 , H03F2203/45134
Abstract: A class AB amplifier may include an input stage, a first folded cascode stage, a second folded cascode stage, and a class AB output stage. In some embodiments, the class AB output stage may provide differential output signals. The common-mode voltage of the differential output signals may be controlled via a correction signal coupled to a selected folded cascode stage. The correction signal may control the common-mode voltage of the differential output signals by altering bias currents within the selected folded cascode stage. The other cascode stage may include bias currents controlled by relatively fixed bias voltages.
Abstract translation: AB类放大器可以包括输入级，第一折叠共源共栅级，第二折叠共源共栅级和AB类输出级。 在一些实施例中，AB类输出级可以提供差分输出信号。 差分输出信号的共模电压可以通过耦合到所选择的折叠共源共栅级的校正信号来控制。 校正信号可以通过改变所选折叠共源共栅级内的偏置电流来控制差分输出信号的共模电压。 另一个共源共栅级可以包括由相对固定的偏置电压控制的偏置电流。
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公开(公告)号：US20210067115A1
公开(公告)日：2021-03-04
申请号：US16560660
申请日：2019-09-04
Applicant: Qualcomm Incorporated
Inventor： Rahul Karmaker , Conor Donovan , Li-chung Chang
Abstract: An apparatus is disclosed for processing a signal with a divided amplifier. In example implementations, an apparatus includes a first portion of an amplifier, a first port interface, a second port interface, and a switch matrix. The first port interface includes a first transformer; a second portion of the amplifier, which is coupled to the first transformer; and a first switch component that is coupled to at least one of the first transformer or the second portion of the amplifier. The second port interface includes a second transformer and a second switch component that is coupled to the second transformer. The switch matrix is coupled between the first switch component and the first portion of the amplifier and between the second switch component and the first portion of the amplifier. The switch matrix is also coupled between the second portion of the amplifier and the first portion of the amplifier.
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公开(公告)号：US10778188B1
公开(公告)日：2020-09-15
申请号：US16283689
申请日：2019-02-22
Applicant: Qualcomm Incorporated
Inventor： Rahul Karmaker
Abstract: An apparatus is disclosed for a harmonic rejection filter with transimpedance amplifiers. In an example aspect, the apparatus includes a harmonic rejection filter with at least three input nodes, at least one output node, a first transimpedance amplifier, a first set of transimpedance amplifiers, and a scaling current converter. The at least three input nodes include a first input node, a second input node, and a third input node. The at least one output node includes a first output node. The first transimpedance amplifier is coupled between the first input node and the first output node. The first set of transimpedance amplifiers include a second transimpedance amplifier coupled to the second input node and a third transimpedance amplifier coupled to the third input node. The scaling current converter is coupled between outputs associated with the first set of transimpedance amplifiers and an input of the first transimpedance amplifier.
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Patent Agency Ranking
6.发明授权公开(公告)号：US09673782B1
公开(公告)日：2017-06-06
申请号：US15238176
申请日：2016-08-16
Applicant: QUALCOMM Incorporated
Inventor： Shuja Andrabi , Rahul Karmaker
CPC classification number: H03H11/1256 , H03H2210/012 , H03H2210/015 , H03H2210/025 , H03H2210/028 , H03H2210/04 , H04B1/005
Abstract: Certain aspects of the present disclosure provide methods and apparatus for calibrating a tunable active filter. One example apparatus is a filter circuit that generally includes a tunable active filter comprising at least one amplifier and a first feedback path coupled between an input and an output of the at least one amplifier, the first feedback path comprising at least one switch; and an amplitude limiter coupled to the tunable active filter and comprising at least one transistor disposed in a second feedback path coupled between the input and the output of the at least one amplifier.
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7.发明授权公开(公告)号：US11962278B2
公开(公告)日：2024-04-16
申请号：US17318959
申请日：2021-05-12
Applicant: QUALCOMM Incorporated
Inventor： Ahmed Abbas Mohamed Helmy , Mehran Bakhshiani , Francesco Gatta , Hasnain Lakdawala , Rahul Karmaker , Shankar Guhados
CPC classification number: H03F3/45475 , H03G3/30 , H03H11/1226 , H03H19/004 , H04B1/0032 , H04B1/0039 , H04B1/0042 , H04B1/0078 , H04B1/1615 , H04B1/18 , H03F2200/129 , H03F2200/165 , H03F2203/45526
Abstract: An aspect includes a filtering method including operating a first filter to filter a first input signal to generate a first output signal; operating a second filter to filter a second input signal to generate a second output signal; and selectively coupling at least a portion of the second filter with the first filter to filter a third input signal to generate a third output signal. Another aspect includes a filtering method including operating switching devices to configure a filter with a first set of pole(s); filtering a first input signal to generate a first output signal with the filter configured with the first set of pole(s); operating the switching devices to configure the filter with a second set of poles; and filtering a second input signal to generate a second output signal with the filter configured with the second set of poles.
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公开(公告)号：US11184039B1
公开(公告)日：2021-11-23
申请号：US16882313
申请日：2020-05-22
Applicant: QUALCOMM Incorporated
Inventor： Rahul Karmaker , Francesco Gatta
Abstract: According to certain aspects, a chip includes a first port, a first amplifier, and a first input path coupling the first port to an input of the first amplifier. The chip also includes a second port, a second amplifier, and a second input path coupling the second port to an input of the second amplifier. The chip further includes a switchable path coupled between the first input path and the second input path.
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公开(公告)号：US20200274522A1
公开(公告)日：2020-08-27
申请号：US16283689
申请日：2019-02-22
Applicant: Qualcomm Incorporated
Inventor： Rahul Karmaker
Abstract: An apparatus is disclosed for a harmonic rejection filter with transimpedance amplifiers. In an example aspect, the apparatus includes a harmonic rejection filter with at least three input nodes, at least one output node, a first transimpedance amplifier, a first set of transimpedance amplifiers, and a scaling current converter. The at least three input nodes include a first input node, a second input node, and a third input node. The at least one output node includes a first output node. The first transimpedance amplifier is coupled between the first input node and the first output node. The first set of transimpedance amplifiers include a second transimpedance amplifier coupled to the second input node and a third transimpedance amplifier coupled to the third input node. The scaling current converter is coupled between outputs associated with the first set of transimpedance amplifiers and an input of the first transimpedance amplifier.
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公开(公告)号：US10425071B2
公开(公告)日：2019-09-24
申请号：US15632238
申请日：2017-06-23
Applicant: QUALCOMM Incorporated
Inventor： Rahul Karmaker
IPC: G05F1/10 , H03F3/16 , H03F3/45 , G01R17/16 , H03F3/193 , H03K5/1532 , G01R19/04 , H03G3/00 , H03K5/153 , H03G1/00 , G11C7/06 , H03F1/52 , H03G3/30
Abstract: The present disclosure describes aspects of a fast settling peak detector. In some aspects, a peak detector circuit includes a first transistor having a gate coupled to an input of the circuit at which a signal is received and a drain coupled to a source of a second transistor. Current may flow in the first and second transistors responsive to the signal. The circuit also includes a third transistor having a gate coupled, via a signal-inverting component, to the input of the circuit and a drain coupled to a source of a fourth transistor. Through an inversion of the signal, other current flowing in the third and fourth transistor can reduce or cancel a frequency component of the current in the first and second transistors. In some cases, this precludes a need to filter the frequency component from an output of the circuit.
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