公开(公告)号：US20240355381A1

公开(公告)日：2024-10-24

申请号：US18306167

申请日：2023-04-24

Applicant: QUALCOMM Incorporated

Inventor： Seohee KIM ,  Chulmin JUNG ,  Xiao CHEN ,  Hanil LEE ,  Venugopal BOYNAPALLI ,  Jung Pill KIM

IPC: G11C11/413 ,  H03K5/24 ,  H10B10/00

CPC classification number: G11C11/413 ,  H03K5/24 ,  H10B10/18

Abstract: An integrated circuit is disclosed that includes a power supply multiplexer for selecting between a first power supply voltage and a second power supply voltage to provide a selected power supply voltage to a memory. A controller includes a comparator stage having a comparator with switchable inputs so that the comparator stage may control a binary state of a first output signal responsive to whether the first power supply voltage is greater than the second power supply voltage plus a voltage offset of the comparator. Similarly, the comparator stage may control a binary state of a second output signal responsive to whether the first power supply voltage is greater than the second power supply voltage minus the voltage offset. The controller controls the selection by the power supply multiplexer responsive to the binary states of the first and second output signals.

公开(公告)号：US20240266342A1

公开(公告)日：2024-08-08

申请号：US18165259

申请日：2023-02-06

Applicant: QUALCOMM Incorporated

Inventor： Renukprasad HIREMATH ,  Hyeokjin LIM ,  Foua VANG ,  Manjanaika CHANDRANAIKA ,  Seung Hyuk KANG ,  Venugopal BOYNAPALLI

IPC: H01L27/02 ,  G06F30/392

CPC classification number: H01L27/0207 ,  G06F30/392

Abstract: A chip includes a first column including first rails extending in a first direction, the first rails having a first pitch. The chip also includes a second column including second rails extending in the first direction, the second rails having a second pitch different from the first pitch. The chip also includes a transition region between the first column and the second column.

公开(公告)号：US20240250669A1

公开(公告)日：2024-07-25

申请号：US18156975

申请日：2023-01-19

Applicant: QUALCOMM Incorporated

Inventor： Ramaprasath VILANGUDIPITCHAI ,  Rui CHEN ,  Seung Hyuk KANG ,  Venugopal BOYNAPALLI

IPC: H03K3/037

CPC classification number: H03K3/0372 ,  H03K3/012

Abstract: A hybrid flop tray, including: a set of flip-flops cascaded along a scan path, wherein a first subset of one or more of the flip-flops of the set includes fin field effect transistors (FinFETs) each sized with a first number of fins, and a second subset of one or more of the flip-flops of the set includes FinFETs each sized with a second number of fins, wherein the first number of fins is different than the second number of fins; and a control circuit configured to provide control signals to the set of flip-flops.

公开(公告)号：US20220068360A1

公开(公告)日：2022-03-03

申请号：US17002082

申请日：2020-08-25

Applicant: QUALCOMM Incorporated

Inventor： Arun Babu PALLERLA ,  Changho JUNG ,  Sung SON ,  Jason CHENG ,  Yandong GAO ,  Chulmin JUNG ,  Venugopal BOYNAPALLI

IPC: G11C11/4096 ,  G11C11/408 ,  G11C11/4094 ,  G11C11/4074 ,  G11C5/02

Abstract: A bitcell architecture for a pseudo-triple-port memory is provided that includes a a bitcell arranged on a semiconductor substrate, the bitcell defining a bitcell width and a bitcell height and including a first access transistor and a second access transistor. A first metal layer adjacent the semiconductor substrate is patterned to form a pair of local bit lines arranged within the bitcell width. The pair of local bit lines includes a local bit line coupled to a terminal of the first access transistor and includes a complement local bit line coupled to a terminal of the second access transistor.

公开(公告)号：US20240249056A1

公开(公告)日：2024-07-25

申请号：US18156999

申请日：2023-01-19

Applicant: QUALCOMM Incorporated

Inventor： Hyeokjin LIM ,  Ankur MEHROTRA ,  Renukprasad HIREMATH ,  Foua VANG ,  Manjanaika CHANDRANAIKA ,  Akhtar ALAM ,  Kamesh MEDISETTI ,  Seung Hyuk KANG ,  Venugopal BOYNAPALLI

IPC: G06F30/392 ,  H01L21/768 ,  H01L23/48 ,  H01L23/498 ,  H01L23/528 ,  H01L27/02

CPC classification number: G06F30/392 ,  H01L21/76898 ,  H01L23/481 ,  H01L23/49827 ,  H01L23/5286 ,  H01L27/0207

Abstract: A chip includes a spare cell including a first active region, and a first gate extending over the first active region in a first direction. The chip also includes a tie cell including a second active region, a second gate extending over the second active region in the first direction, a first drain contact formed over the second active region, a first source contact formed over the second active region, wherein the second gate is between the first drain contact and the first source contact, and first source contact is coupled to a first rail, and a circuit configured to couple the second gate to a second rail. The chip also includes a metal routing extending in a second direction, wherein the second direction is perpendicular to the first direction, and the first metal routing is coupled to the first drain contact and the first gate.

公开(公告)号：US20220115405A1

公开(公告)日：2022-04-14

申请号：US17065746

申请日：2020-10-08

Applicant: QUALCOMM Incorporated

Inventor： Hyeokjin LIM ,  Venugopal BOYNAPALLI ,  Foua VANG ,  Seung Hyuk KANG

IPC: H01L27/118

Abstract: A MOS IC includes first and second sets of adjacent transistor logic, each of which include collinear gate interconnects extending in a first direction with the same gate pitch. The first set of transistor logic has a first cell height h1 and a first number of Mx layer tracks that extend unidirectionally in a second direction orthogonal to the first direction. The second set of transistor logic has a second cell height h2 and a second number of Mx layer tracks that extend unidirectionally in the second direction, where h2>h1 and the second number of Mx layer tracks is greater than the first number of Mx layer tracks. At least one of a height ratio hR=h2/h1 is a non-integer value or a subset of the first set of transistor logic and a subset of the second set of transistor logic are within one logic cell.

公开(公告)号：US20180183439A1

公开(公告)日：2018-06-28

申请号：US15393180

申请日：2016-12-28

Applicant: QUALCOMM Incorporated

Inventor： Satyanarayana SAHU ,  Xiangdong CHEN ,  Venugopal BOYNAPALLI ,  Hyeokjin LIM ,  Mickael MALABRY ,  Mukul GUPTA

IPC: H03K19/0948 ,  H01L27/118 ,  H01L23/528 ,  H01L23/522

CPC classification number: H03K19/0948 ,  H01L23/522 ,  H01L23/5226 ,  H01L23/528 ,  H01L27/0207 ,  H01L27/0924 ,  H01L27/11807 ,  H01L2027/11853 ,  H01L2027/11875 ,  H01L2027/11887 ,  H01L2027/11888

Abstract: A MOS device of an IC includes pMOS and nMOS transistors. The MOS device further includes a first Mx layer interconnect extending in a first direction and coupling the pMOS and nMOS transistor drains together, and a second Mx layer interconnect extending in the first direction and coupling the pMOS and nMOS transistor drains together. The first and second Mx layer interconnects are parallel. The MOS device further includes a first Mx+1 layer interconnect extending in a second direction orthogonal to the first direction. The first Mx+1 layer interconnect is coupled to the first Mx layer interconnect and the second Mx layer interconnect. The MOS device further includes a second Mx+1 layer interconnect extending in the second direction. The second Mx+1 layer interconnect is coupled to the first Mx layer interconnect and the second Mx layer interconnect. The second Mx+1 layer interconnect is parallel to the first Mx+1 layer interconnect.

公开(公告)号：US20170237434A1

公开(公告)日：2017-08-17

申请号：US15044988

申请日：2016-02-16

Applicant: QUALCOMM Incorporated

Inventor： Qi YE ,  Animesh DATTA ,  Venkatasubramanian NARAYANAN ,  Venugopal BOYNAPALLI

IPC: H03K19/003 ,  H03K3/037

CPC classification number: H03K19/00384 ,  H03K3/033 ,  H03K3/0375 ,  H03K5/04

Abstract: The apparatus may include a first latch configured to store a first state or a second state. The first latch may have a first latch input, one of a set input or a reset input, a first pulse clock input, and a first latch output. The first latch input may be coupled to a fixed logic value. The one of the set input or the reset input may be coupled to a clock signal or an inverted clock signal, respectively. The apparatus may include an AND gate having a first AND gate input, a second AND gate input, and a first AND gate output. The clock signal may be coupled to the first AND gate input. The first latch output may be coupled to the second AND gate input. The AND gate output may be configured to output a pulsed clock. The pulsed clock may be coupled to the first pulse clock input.

公开(公告)号：US20240170488A1

公开(公告)日：2024-05-23

申请号：US17993594

申请日：2022-11-23

Applicant: QUALCOMM Incorporated

Inventor： Renukprasad HIREMATH ,  Keyurkumar Karsanbhai KANSAGRA ,  Shashikumar GANESH BHAT ,  Hyeokjin LIM ,  Seung Hyuk KANG ,  Venugopal BOYNAPALLI ,  Kamesh MEDISETTI

IPC: H01L27/118 ,  H03K19/094

CPC classification number: H01L27/11807 ,  H03K19/094 ,  H01L2027/11866 ,  H01L2027/11875 ,  H01L2027/11881 ,  H01L2027/11885

Abstract: An integrated circuit (IC) cell including: a first logic gate comprising a first polysilicon structure and a first pin; a second logic gate comprising a second polysilicon structure and a second pin, wherein the second polysilicon structure is spaced apart and adjacent to the first polysilicon structure in a cell row direction; and a source region, common to the first and second logic gates, situated between the first and second polysilicon structures, wherein the first and second pins are on a first metal track directly over the common source region.

公开(公告)号：US20220094363A1

公开(公告)日：2022-03-24

申请号：US17030087

申请日：2020-09-23

Applicant: QUALCOMM Incorporated

Inventor： Foua VANG ,  Hyeokjin LIM ,  Seung Hyuk KANG ,  Venugopal BOYNAPALLI ,  Shitiz ARORA

IPC: H03K19/094 ,  H01L23/528

Abstract: A MOS IC includes a MOS logic cell that includes first and second sets of transistor logic in first and second subcells, respectively. The first and second sets of transistor logic are functionally isolated from each other. The MOS logic cell includes a first set of Mx layer interconnects on an Mx layer extending in a first direction over the first and second subcells. A first subset of the first set of Mx layer interconnects is coupled to inputs/outputs of the first set of transistor logic in the first subcell and is unconnected to the second set of transistor logic. Each of the first subset of the first set of Mx layer interconnects extends from the corresponding input/output of the first set of transistor logic of the first subcell to the second subcell, and is the corresponding input/output of the first set of transistor logic.