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公开(公告)号：US10678459B2
公开(公告)日：2020-06-09
申请号：US15745396
申请日：2016-07-14
Applicant: Rambus Inc.
Inventor： Suresh Rajan , Abhijit M. Abhyankar , Ravindranath Kollipara , David A. Secker
Abstract: Described are memory modules that include address-buffer components and data-buffer components that together support wide- and narrow-data modes. The address-buffer component manages communication between a memory controller and two sets of memory components. In the wide-data mode, the address-buffer enables memory components in each set and instructs the data-buffer components to communicate full-width read and write data by combining data from or to from both sets for each memory access. In the narrow-data mode, the address-buffer enables memory components in just one of the two sets and instructs the data-buffer components to half-width read and write data with one set per memory access.
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公开(公告)号：US10380053B2
公开(公告)日：2019-08-13
申请号：US15289785
申请日：2016-10-10
Applicant: Rambus Inc.
Inventor： Amir Amirkhany , Suresh Rajan , Ravindranath Kollipara , Ian Shaeffer , David A. Secker
Abstract: A memory module comprises a data interface including a plurality of data lines and a plurality of configurable switches coupled between the data interface and a data path to one or more memories. The effective width of the memory module can be configured by enabling or disabling different subsets of the configurable switches. The configurable switches may be controlled by manual switches, by a buffer on the memory module, by an external memory controller, or by the memories on the memory module.
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公开(公告)号：US09281816B2
公开(公告)日：2016-03-08
申请号：US14368772
申请日：2012-12-22
Applicant: Rambus Inc.
Inventor： Amir Amirkhany , Farshid Aryanfar , Ravindranath Kollipara , Xingchao (Chuck) Yuan
IPC: H03K19/00 , H03K19/0175 , H04L25/02 , G11C29/50 , G06F13/40
CPC classification number: H03K19/0005 , G06F13/4086 , G11C29/50008 , H03K19/017545 , H04L25/0278
Abstract: Alternating on-die termination impedances are applied within an integrated circuit device to up-convert signal reflections to higher frequencies that are attenuated by the signaling channel as the reflections propagate toward an intended signal receiver. Through this approach, the disruptive effect of reflected signals may be significantly reduced with relatively little overhead within the interconnected integrated circuit devices and little or no change to the printed circuit board or other interconnect medium. Changes to the printed circuit board or other interconnect medium can be made to further increase attenuation over the frequency band of the up-converted reflection and outside of the transmission band of signals of interest.
Abstract translation: 在集成电路器件内施加交替的片上终端阻抗，以将信号反射上变频到由信号通道衰减的较高频率，因为反射向预期信号接收器传播。 通过这种方法，相互连接的集成电路器件内的相对较少的开销可以显着降低反射信号的破坏性影响，并且对印刷电路板或其它互连介质几乎没有或没有改变。 可以对印刷电路板或其它互连介质进行改变，以进一步增加在上变频反射的频带和感兴趣的信号的传输频带之外的衰减。
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公开(公告)号：US20130258755A1
公开(公告)日：2013-10-03
申请号：US13845503
申请日：2013-03-18
Applicant: RAMBUS, INC.
Inventor： Ravindranath Kollipara , Lei Luo , Ian Shaeffer
IPC: G11C11/401
CPC classification number: G11C11/401 , G11C5/04 , G11C7/1057 , G11C7/1084
Abstract: An embodiment is directed to an integrated circuit device having programmable input capacitance. For example, a programmable register of a memory device may store a value representative of an adjustment to the input capacitance value of a control pin. An embodiment is directed to controlling the skew of a synchronous memory system by allowing programmability of the lighter loaded pins in order to increase their load to match the more heavily loaded pins. By matching lighter loaded pins to more heavily loaded pins, the system exhibits improved synchronization of propagation delays of the control and address pins. In addition, an embodiment provides the ability to vary the loading depending on how many ranks are on the device.
Abstract translation: 实施例涉及具有可编程输入电容的集成电路器件。 例如，存储器件的可编程寄存器可以存储代表控制引脚的输入电容值的调整值。 一个实施例旨在通过允许较轻负载的引脚的可编程性来控制同步存储器系统的偏斜，以便增加它们的负载以匹配负载较重的引脚。 通过将较轻负载的引脚匹配到负载较重的引脚，系统表现出改进的控制和地址引脚的传播延迟同步。 此外，实施例提供了根据设备上多少等级来改变负载的能力。
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公开(公告)号：US12147367B2
公开(公告)日：2024-11-19
申请号：US18355660
申请日：2023-07-20
Applicant: Rambus Inc.
Inventor： Amir Amirkhany , Suresh Rajan , Ravindranath Kollipara , Ian Shaeffer , David A. Secker
Abstract: A memory module comprises a data interface including a plurality of data lines and a plurality of configurable switches coupled between the data interface and a data path to one or more memories. The effective width of the memory module can be configured by enabling or disabling different subsets of the configurable switches. The configurable switches may be controlled by manual switches, by a buffer on the memory module, by an external memory controller, or by the memories on the memory module.
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Patent Agency Ranking
公开(公告)号：US20230138512A1
公开(公告)日：2023-05-04
申请号：US17989838
申请日：2022-11-18
Applicant: Rambus Inc.
Inventor： Suresh Rajan , Abhijit M. Abhyankar , Ravindranath Kollipara , David A. Secker
Abstract: Described are memory modules that include address-buffer components and data-buffer components that together support wide- and narrow-data modes. The address-buffer component manages communication between a memory controller and two sets of memory components. In the wide-data mode, the address-buffer enables memory components in each set and instructs the data-buffer components to communicate full-width read and write data by combining data from or to from both sets for each memory access. In the narrow-data mode, the address-buffer enables memory components in just one of the two sets and instructs the data-buffer components to half-width read and write data with one set per memory access.
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公开(公告)号：US20210124703A1
公开(公告)日：2021-04-29
申请号：US16950861
申请日：2020-11-17
Applicant: Rambus Inc.
Inventor： Amir Amirkhany , Suresh Rajan , Ravindranath Kollipara , Ian Shaeffer , David A. Secker
Abstract: A memory module comprises a data interface including a plurality of data lines and a plurality of configurable switches coupled between the data interface and a data path to one or more memories. The effective width of the memory module can be configured by enabling or disabling different subsets of the configurable switches. The configurable switches may be controlled by manual switches, by a buffer on the memory module, by an external memory controller, or by the memories on the memory module.
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公开(公告)号：US09798628B2
公开(公告)日：2017-10-24
申请号：US14568848
申请日：2014-12-12
Applicant: Rambus Inc.
Inventor： Steven Woo , David Secker , Ravindranath Kollipara
CPC classification number: G06F11/1456 , G06F1/12 , G06F11/1666 , G06F11/20 , G06F11/2058 , G06F13/4234 , G06F2201/84
Abstract: Memory system enabling memory mirroring in single write operations. The memory system includes a memory channel which can store duplicate copies of a data element into multiple locations in the memory channel. The multiple locations are disposed in different memory modules and have different propagation times with respect to a data signal transmitted from the memory controller. In a write operation, the relative timings of the chip select, command and address signals among the multiple locations are adjusted according to the data propagation delay. As a result, a data element can be written into the multiple locations responsive to a data signal transmitted from the memory controller in a single transmission event.
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公开(公告)号：US20250103531A1
公开(公告)日：2025-03-27
申请号：US18919179
申请日：2024-10-17
Applicant: Rambus Inc.
Inventor： Amir Amirkhany , Suresh Rajan , Ravindranath Kollipara , Ian Shaeffer , David A. Secker
Abstract: A memory module comprises a data interface including a plurality of data lines and a plurality of configurable switches coupled between the data interface and a data path to one or more memories. The effective width of the memory module can be configured by enabling or disabling different subsets of the configurable switches. The configurable switches may be controlled by manual switches, by a buffer on the memory module, by an external memory controller, or by the memories on the memory module.
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公开(公告)号：US20240220141A1
公开(公告)日：2024-07-04
申请号：US18419933
申请日：2024-01-23
Applicant: Rambus Inc.
Inventor： Suresh Rajan , Abhijit M. Abhyankar , Ravindranath Kollipara , David A. Secker
CPC classification number: G06F3/0635 , G06F3/0613 , G06F3/0656 , G06F3/0673 , G06F13/1678 , Y02D10/00
Abstract: Described are memory modules that include address-buffer components and data-buffer components that together support wide- and narrow-data modes. The address-buffer component manages communication between a memory controller and two sets of memory components. In the wide-data mode, the address-buffer enables memory components in each set and instructs the data-buffer components to communicate full-width read and write data by combining data from or to from both sets for each memory access. In the narrow-data mode, the address-buffer enables memory components in just one of the two sets and instructs the data-buffer components to half-width read and write data with one set per memory access.
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