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公开(公告)号：US20180145693A1
公开(公告)日：2018-05-24
申请号：US15796608
申请日：2017-10-27
Applicant: Rambus Inc.
Inventor： Marko Aleksic , Brian S. Leibowitz
CPC classification number: H03L1/00 , H03K3/0315 , H03L7/083 , H03L7/24
Abstract: A variable injection-strength injection-locked oscillator (ILO) is described. The variable injection-strength ILO can output an output clock signal based on an input clock signal. The variable injection-strength ILO can pause, restart, slow down, or speed up the output clock signal synchronously with respect to the input clock signal in response to receiving power mode information. Specifically, the variable injection-strength ILO can be operated under relatively strong injection when the input clock signal is paused, restarted, slowed down, or sped up.
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2.发明申请公开(公告)号：US20170207790A1
公开(公告)日：2017-07-20
申请号：US15390350
申请日：2016-12-23
Applicant: Rambus Inc.
Inventor： Marko Aleksic , Brian S. Leibowitz
CPC classification number: H03L7/24 , H03K5/26 , H03K2005/00286 , H03L7/081 , H03L7/099 , H03L7/0995
Abstract: Methods and apparatuses featuring an injection-locked oscillator (ILO) are described. In some embodiments, an ILO can have multiple injection points and a free-running frequency that is capable of being adjusted based on a control signal. In some embodiments, each injection point of an ILO can correspond to a phase tuning range. In some embodiments, a circuit can include circuitry to detect a phase boundary between two adjacent phase tuning ranges. In some embodiments, a circuit can use the detected phase boundary to switch between the two adjacent phase tuning ranges.
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公开(公告)号：US20170005785A1
公开(公告)日：2017-01-05
申请号：US15176864
申请日：2016-06-08
Applicant: Rambus Inc.
Inventor： Marko Aleksic , Simon Li , Roxanne Vu
CPC classification number: H04L7/033 , H03L7/081 , H04L7/0004 , H04L7/0079 , H04L7/0337 , H04L25/03
Abstract: A receiver with clock phase calibration. A first sampling circuit generates first digital data based on an input signal, a sampling phase of the first sampling circuit controlled by a first clock signal. A second sampling circuit generates second digital data based on the input signal, a sampling phase of the second sampling circuit controlled by a second clock signal. Circuitry within the receiver calibrates the clocks in different stages. During a first calibration stage, a phase of the second clock signal is adjusted while the first digital data is selected for generating the output data. During a second calibration stage, a phase of the first clock signal is adjusted while the first digital data is selected for the output data path.
Abstract translation: 具有时钟相位校准的接收器。 第一采样电路基于输入信号，由第一时钟信号控制的第一采样电路的采样相位产生第一数字数据。 第二采样电路基于输入信号产生第二数字数据，由第二时钟信号控制的第二采样电路的采样相位。 接收机内的电路校准不同阶段的时钟。 在第一校准阶段期间，在选择第一数字数据以产生输出数据的同时调整第二时钟信号的相位。 在第二校准阶段期间，在为输出数据路径选择第一数字数据的同时调整第一时钟信号的相位。
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公开(公告)号：US11184198B2
公开(公告)日：2021-11-23
申请号：US16811353
申请日：2020-03-06
Applicant: Rambus Inc.
Inventor： Marko Aleksic , Pravin Kumar Venkatesan , Simon Li , Nikhil Vaidya
Abstract: A receiver includes a decision circuit, a circuit to adjust an input signal of the decision circuit, a correction circuit and a control circuit. The decision circuit makes a data decision based on an input signal of the decision circuit. The circuit to adjust the input signal of the decision circuit adjusts the input signal of the decision circuit based on an input correction signal. The correction circuit combines a plurality of signals corresponding to different input correction parameters into a preliminary input correction signal. An input of the correction circuit is coupled to an output of the decision circuit. The control circuit maps the preliminary input correction signal into the input correction signal using a nonlinear code mapping.
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公开(公告)号：US10601615B2
公开(公告)日：2020-03-24
申请号：US16161547
申请日：2018-10-16
Applicant: Rambus Inc.
Inventor： Marko Aleksic , Pravin Kumar Venkatesan , Simon Li , Nikhil Vaidya
Abstract: A receiver includes a decision circuit, a circuit to adjust an input signal of the decision circuit, a correction circuit and a control circuit. The decision circuit makes a data decision based on an input signal of the decision circuit. The circuit to adjust the input signal of the decision circuit adjusts the input signal of the decision circuit based on an input correction signal. The correction circuit combines a plurality of signals corresponding to different input correction parameters into a preliminary input correction signal. An input of the correction circuit is coupled to an output of the decision circuit. The control circuit maps the preliminary input correction signal into the input correction signal using a nonlinear code mapping.
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Patent Agency Ranking
6.发明授权Integrated circuit having a clock deskew circuit that includes an injection-locked oscillator 有权具有包括注入锁定振荡器的时钟偏移电路的集成电路公开(公告)号：US09264055B2
公开(公告)日：2016-02-16
申请号：US14444669
申请日：2014-07-28
Applicant: Rambus Inc.
Inventor： Marko Aleksic , Brian S. Leibowitz
CPC classification number: H03L7/24 , H03K5/26 , H03K2005/00286 , H03L7/081 , H03L7/099 , H03L7/0995
Abstract: Methods and apparatuses featuring an injection-locked oscillator (ILO) are described. In some embodiments, an ILO can have multiple injection points and a free-running frequency that is capable of being adjusted based on a control signal. In some embodiments, each injection point of an ILO can correspond to a phase tuning range. In some embodiments, a circuit can include circuitry to detect a phase boundary between two adjacent phase tuning ranges. In some embodiments, a circuit can use the detected phase boundary to switch between the two adjacent phase tuning ranges.
Abstract translation: 描述了具有注入锁定振荡器（ILO）的方法和装置。 在一些实施例中，国际劳工组织可以具有多个注入点和能够基于控制信号进行调整的自由运行频率。 在一些实施例中，ILO的每个注入点可以对应于相位调谐范围。 在一些实施例中，电路可以包括用于检测两个相邻相位调谐范围之间的相位边界的电路。 在一些实施例中，电路可以使用所检测的相位边界在两个相邻相位调谐范围之间切换。
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公开(公告)号：US20140313387A1
公开(公告)日：2014-10-23
申请号：US14355814
申请日：2012-11-08
Applicant: RAMBUS INC.
Inventor： Thomas Vogelsang , David Geoffrey Stork , Jie Shen , Yueyong Wang , Marko Aleksic
IPC: H04N5/353 , H04N5/3745 , H04N5/369
CPC classification number: H04N5/353 , H04N5/3355 , H04N5/3696 , H04N5/37455 , H04N5/37457
Abstract: In an integrated-circuit image sensor, binary sample values are read out from an array of pixels after successive sampling intervals that collectively span an image exposure interval and include at least two sampling intervals of unequal duration. Each pixel of the array is conditionally reset after each of the successive sampling intervals according to whether the pixel yields a binary sample in a first state or a second state.
Abstract translation: 在集成电路图像传感器中，在连续的采样间隔之后从像素阵列中读出二进制采样值，该采样间隔共同跨越图像曝光间隔并且包括至少两个不等长度的采样间隔。 根据该像素是否产生处于第一状态或第二状态的二进制样本，阵列的每个像素在每个连续采样间隔之后有条件地重置。
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公开(公告)号：US20200295974A1
公开(公告)日：2020-09-17
申请号：US16811353
申请日：2020-03-06
Applicant: Rambus Inc.
Inventor： Marko Aleksic , Pravin Kumar Venkatesan , Simon Li , Nikhil Vaidya
Abstract: A receiver includes a decision circuit, a circuit to adjust an input signal of the decision circuit, a correction circuit and a control circuit. The decision circuit makes a data decision based on an input signal of the decision circuit. The circuit to adjust the input signal of the decision circuit adjusts the input signal of the decision circuit based on an input correction signal. The correction circuit combines a plurality of signals corresponding to different input correction parameters into a preliminary input correction signal. An input of the correction circuit is coupled to an output of the decision circuit. The control circuit maps the preliminary input correction signal into the input correction signal using a nonlinear code mapping.
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公开(公告)号：US20180013544A1
公开(公告)日：2018-01-11
申请号：US15659394
申请日：2017-07-25
Applicant: Rambus Inc.
Inventor： Marko Aleksic , Simon Li , Roxanne Vu
CPC classification number: H04L7/033 , H03L7/081 , H04L7/0004 , H04L7/0079 , H04L7/0337 , H04L25/03
Abstract: A receiver with clock phase calibration. A first sampling circuit generates first digital data based on an input signal, a sampling phase of the first sampling circuit controlled by a first clock signal. A second sampling circuit generates second digital data based on the input signal, a sampling phase of the second sampling circuit controlled by a second clock signal. Circuitry within the receiver calibrates the clocks in different stages. During a first calibration stage, a phase of the second clock signal is adjusted while the first digital data is selected for generating the output data. During a second calibration stage, a phase of the first clock signal is adjusted while the first digital data is selected for the output data path.
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10.发明申请INTEGRATED CIRCUIT HAVING A CLOCK DESKEW CIRCUIT THAT INCLUDES AN INJECTION-LOCKED OSCILLATOR 有权具有包括注射锁定振荡器的时钟电路的集成电路公开(公告)号：US20160226504A1
公开(公告)日：2016-08-04
申请号：US14990443
申请日：2016-01-07
Applicant: Rambus Inc.
Inventor： Marko Aleksic , Brian S. Leibowitz
CPC classification number: H03L7/24 , H03K5/26 , H03K2005/00286 , H03L7/081 , H03L7/099 , H03L7/0995
Abstract: Methods and apparatuses featuring an injection-locked oscillator (ILO) are described. In some embodiments, an ILO can have multiple injection points and a free-running frequency that is capable of being adjusted based on a control signal. In some embodiments, each injection point of an ILO can correspond to a phase tuning range. In some embodiments, a circuit can include circuitry to detect a phase boundary between two adjacent phase tuning ranges. In some embodiments, a circuit can use the detected phase boundary to switch between the two adjacent phase tuning ranges.
Abstract translation: 描述了具有注入锁定振荡器（ILO）的方法和装置。 在一些实施例中，国际劳工组织可以具有多个注入点和能够基于控制信号进行调整的自由运行频率。 在一些实施例中，ILO的每个注入点可以对应于相位调谐范围。 在一些实施例中，电路可以包括用于检测两个相邻相位调谐范围之间的相位边界的电路。 在一些实施例中，电路可以使用所检测的相位边界在两个相邻相位调谐范围之间切换。
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