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公开(公告)号：US20250030422A1
公开(公告)日：2025-01-23
申请号：US18353996
申请日：2023-07-18
Applicant: Raytheon Company
Inventor： Micky R. Harris , Magathi J. Willis
IPC: H03K19/0185
Abstract: An apparatus includes an input circuit configured to level-shift an input signal and generate an output signal having a voltage range different than a voltage range of the input signal. The input circuit includes (i) a blocking gate configured to level shift the input signal and (ii) an inverter or buffer configured to generate the output signal based on an output of the blocking gate. The input circuit is configured to generate the output signal such that the voltage range of the output signal spans between a first voltage provided to the inverter or buffer and a second voltage provided to the inverter or buffer. The blocking gate may include a transistor, a source or drain of the transistor may be configured to receive the input signal, and a gate of the transistor may be configured to receive the first voltage. The first voltage may include a core voltage of an integrated circuit device.
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2.发明申请公开(公告)号：US20210105425A1
公开(公告)日：2021-04-08
申请号：US17091689
申请日：2020-11-06
Applicant: RAYTHEON COMPANY
Inventor： Steven Botts , Bryan W. Kean , Richard J. Peralta , John L. Vampola , Micky R. Harris
Abstract: A TDI scanner including a dynamically programmable focal plane array including a two-dimensional array of detectors arranged in a plurality of columns and a plurality of rows, the array being divided into a plurality of banks separated from one another by gap regions, each bank including a plurality of sub-banks, and each sub-bank including at least one row of detectors, a ROIC coupled to the focal plane array and configured to combine in a TDI process outputs from detectors in each column of detectors in each sub-bank, and a controller configured to program the focal plane array to selectively and dynamically set characteristics of the focal plane array, the characteristics including a size and a location within the two-dimensional array of each of the plurality of sub-banks and the gap regions, the size corresponding to a number of rows of detectors included in the respective sub-bank or gap region.
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3.发明申请公开(公告)号：US20150215536A1
公开(公告)日：2015-07-30
申请号：US14167194
申请日：2014-01-29
Applicant: RAYTHEON COMPANY
Inventor： David Buell , John L. Vampola , Micky R. Harris , Steven Botts
CPC classification number: H04N5/23245 , H04N5/2257 , H04N5/2259 , H04N5/257 , H04N5/33 , H04N5/378 , H04N9/09 , H04N9/10 , H04N2201/0452 , H04N2201/0458 , H04N2209/048
Abstract: A combined scanning and staring (SCARING) focal plane array (FPA) imaging system having a plurality of modes of operation is provided. In one example, the SCARING FPA system includes a photodetector array with a plurality of photodetectors arranged in a plurality of photodetector rows, a readout integrated circuit (ROIC) coupled to the photodetector array, and a processor coupled to the ROIC. The processor coupled to the ROIC is configured to dynamically configure the SCARING FPA between a scanning mode of operation and a staring mode of operation.
Abstract translation: 提供具有多种操作模式的组合扫描和盯着（SCARING）焦平面阵列（FPA）成像系统。 在一个示例中，SCARING FPA系统包括具有布置在多个光电检测器行中的多个光电检测器的光电检测器阵列，耦合到光电检测器阵列的读出集成电路（ROIC）和耦合到ROIC的处理器。 耦合到ROIC的处理器被配置为在扫描操作模式和盯着操作模式之间动态地配置SCARING FPA。
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公开(公告)号：US20250030423A1
公开(公告)日：2025-01-23
申请号：US18354034
申请日：2023-07-18
Applicant: Raytheon Company
Inventor： Micky R. Harris , Magathi J. Willis
IPC: H03K19/0185
Abstract: An apparatus includes an output circuit configured to level-shift an incoming signal and generate an output signal having a voltage range different than a voltage range of the incoming signal. The output circuit includes an output driver configured to receive the incoming signal and generate the output signal at a specified voltage level. The output circuit also includes a switched source follower coupled to the output driver. The switched source follower is configured to receive the incoming signal and set the specified voltage level. The switched source follower may include first and second transistors, and the output driver may include a third transistor. The first and third transistors may be configured to be driven by the incoming signal. The second transistor may be configured to be driven by a gate voltage, and the specified voltage level for the output driver may be based on the gate voltage.
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5.发明授权公开(公告)号：US11463639B2
公开(公告)日：2022-10-04
申请号：US17091689
申请日：2020-11-06
Applicant: RAYTHEON COMPANY
Inventor： Steven Botts , Bryan W. Kean , Richard J. Peralta , John L. Vampola , Micky R. Harris
Abstract: A TDI scanner including a dynamically programmable focal plane array including a two-dimensional array of detectors arranged in a plurality of columns and a plurality of rows, the array being divided into a plurality of banks separated from one another by gap regions, each bank including a plurality of sub-banks, and each sub-bank including at least one row of detectors, a ROIC coupled to the focal plane array and configured to combine in a TDI process outputs from detectors in each column of detectors in each sub-bank, and a controller configured to program the focal plane array to selectively and dynamically set characteristics of the focal plane array, the characteristics including a size and a location within the two-dimensional array of each of the plurality of sub-banks and the gap regions, the size corresponding to a number of rows of detectors included in the respective sub-bank or gap region.
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Patent Agency Ranking
6.发明申请公开(公告)号：US20190373194A1
公开(公告)日：2019-12-05
申请号：US16426863
申请日：2019-05-30
Applicant: RAYTHEON COMPANY
Inventor： Steven Botts , Bryan W. Kean , Richard J. Peralta , John L. Vampola , Micky R. Harris
Abstract: A TDI scanner including a dynamically programmable focal plane array including a two-dimensional array of detectors arranged in a plurality of columns and a plurality of rows, the array being divided into a plurality of banks separated from one another by gap regions, each bank including a plurality of sub-banks, and each sub-bank including at least one row of detectors, a ROIC coupled to the focal plane array and configured to combine in a TDI process outputs from detectors in each column of detectors in each sub-bank, and a controller configured to program the focal plane array to selectively and dynamically set characteristics of the focal plane array, the characteristics including a size and a location within the two-dimensional array of each of the plurality of sub-banks and the gap regions, the size corresponding to a number of rows of detectors included in the respective sub-bank or gap region.
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7.发明申请公开(公告)号：US20190180113A1
公开(公告)日：2019-06-13
申请号：US16279182
申请日：2019-02-19
Applicant: Raytheon Company
Inventor： Micky R. Harris , Eric J. Beuville , Juliette S. Costa , Christian M. Boemler , Mark A. Massie
IPC: G06K9/00 , G01J1/02 , H04N1/409 , H04N5/14 , H04N5/355 , G01S17/02 , H04N5/369 , H04N5/3745 , G01T1/17
Abstract: A method includes repeatedly charging and discharging a capacitor, where the capacitor is charged based on illumination received at a pixel. The method also includes comparing a voltage stored on the capacitor with a reference voltage using a comparator. The method further includes incrementing or decrementing a first counter value of a first counter each time a comparator output indicates that the capacitor voltage has reached the reference voltage during a first period of time. The method also includes incrementing or decrementing a second counter value of a second counter each time the comparator output indicates that the capacitor voltage has reached the reference voltage during multiple smaller second periods of time within the first period of time. In addition, the method includes resetting the second counter for each second period of time and generating a pixel event indicator in response to the second counter value obtaining a value indicative of a bright intensity event.
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公开(公告)号：US10063797B2
公开(公告)日：2018-08-28
申请号：US15388023
申请日：2016-12-22
Applicant: RAYTHEON COMPANY
Inventor： John L. Vampola , Micky R. Harris , Bryan W. Kean , Steven Botts , Richard J. Peralta
CPC classification number: H04N5/3559 , H04N5/3535 , H04N5/35527 , H04N5/3742 , H04N5/37452 , H04N5/378
Abstract: According to one aspect, embodiments herein provide a unit cell circuit comprising a photodetector configured to generate a photo-current in response to receiving light, a first integration capacitor configured to accumulate charge corresponding to the photo-current, a second integration capacitor configured to accumulate charge corresponding to the photo-current, a charge diverting switch coupled to the photodetector and configured to selectively couple the first integration capacitor to the second integration capacitor and divert the photo-current to the second integration capacitor in response to a voltage across the first integration capacitor exceeding a threshold level, and read-out circuitry coupled to the first integration capacitor and the charge diverting switch and configured to read-out a first voltage sample from the first integration capacitor corresponding to charge accumulated on the first integration capacitor and to read-out a second voltage sample from the second integration capacitor corresponding to charge accumulated on the second integration capacitor.
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公开(公告)号：US20250030428A1
公开(公告)日：2025-01-23
申请号：US18223365
申请日：2023-07-18
Applicant: RAYTHEON COMPANY
Inventor： Magathi Willis , Micky R. Harris
Abstract: A system for automatically calibrating a phase locked loop (PLL), the system comprising: a node a voltage controlled oscillator (VCO) coupled to the node and configured to provide an output signal to the node; at least one digital-to-analog converter (DAC) coupled to the VCO and configured to provide a voltage to the VCO; and at least one controller configured to: determine an output frequency of the output signal; responsive to determining the output frequency, compare the output frequency to the voltage; responsive to determining the output frequency, compare the output frequency to a target frequency; and control the DAC to modify the voltage based on a comparison of the output frequency to the voltage and a comparison of the output frequency to the target frequency.
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公开(公告)号：US11456746B2
公开(公告)日：2022-09-27
申请号：US16749295
申请日：2020-01-22
Applicant: RAYTHEON COMPANY
Inventor： Richard E. Wahl , Joshua J. Cantrell , John L. Vampola , Micky R. Harris
Abstract: An analog counter circuit for use with a digital pixel includes: an input; an output; a first stage electrically coupled to the input that is charged to an initial charge voltage; a second stage that includes an accumulating charge storage device; and a charge transfer device between the first and second stages that includes a transfer voltage. The charge transfer device allows charge from the first stage to pass to the second stage and be accumulated on the accumulating charge storage device as long as a voltage at a node in the first stage is greater than the transfer voltage.
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