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公开(公告)号：US20220157881A1
公开(公告)日：2022-05-19
申请号：US16952783
申请日：2020-11-19
Applicant: RAYTHEON COMPANY
Inventor： Jamal I. Mustafa , Robert C. Anderson , John L. Vampola , Sean P. Kilcoyne , Eric R. Miller , George Grama
IPC: H01L27/146
Abstract: A direct-bond hybridization (DBH) method is provided to assemble a sensor wafer device. The DBH method includes fabricating an optical element on a handle wafer and depositing first oxide with n-x thickness on the optical element where n is an expected final oxide thickness of the sensor wafer, depositing second oxide with x thickness onto a sensor wafer, executing layer transfer of the optical element by a DBH fusion bond technique to the sensor wafer whereby the first and second oxides form an oxide layer of n thickness between the optical element and the sensor wafer and removing the handle wafer.
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公开(公告)号：US11284025B2
公开(公告)日：2022-03-22
申请号：US16890483
申请日：2020-06-02
Applicant: Raytheon Company
Inventor： Neil R. Malone , Micky Harris , Adam M. Kennedy , George Paloczi , John L. Vampola , Christian M. Boemler
IPC: H04N5/355 , H04N5/378 , H04N5/3745
Abstract: A digital pixel includes a capacitive transimpedance amplifier (CTIA) coupled to a photodiode that receives an electrical charge and output an integration voltage. An integration capacitor coupled to the CTIA accumulates the integration voltage over an integration period. A comparator compares the accumulated integration voltage with a threshold voltage and generates a control signal at a first level each time the accumulated integration voltage is greater than the threshold voltage. A charge subtraction circuit receives the control signal at the first level and discharges the accumulated integration voltage each time the control signal at the first level is received from the comparator. An analog or digital counter receives the control signal at the first level and adjusts a counter value each time the control signal is received from the comparator. An output interface communicates the counter value to an image processing circuit at an end of the integration period.
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3.发明申请公开(公告)号：US20210105425A1
公开(公告)日：2021-04-08
申请号：US17091689
申请日：2020-11-06
Applicant: RAYTHEON COMPANY
Inventor： Steven Botts , Bryan W. Kean , Richard J. Peralta , John L. Vampola , Micky R. Harris
Abstract: A TDI scanner including a dynamically programmable focal plane array including a two-dimensional array of detectors arranged in a plurality of columns and a plurality of rows, the array being divided into a plurality of banks separated from one another by gap regions, each bank including a plurality of sub-banks, and each sub-bank including at least one row of detectors, a ROIC coupled to the focal plane array and configured to combine in a TDI process outputs from detectors in each column of detectors in each sub-bank, and a controller configured to program the focal plane array to selectively and dynamically set characteristics of the focal plane array, the characteristics including a size and a location within the two-dimensional array of each of the plurality of sub-banks and the gap regions, the size corresponding to a number of rows of detectors included in the respective sub-bank or gap region.
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4.发明申请公开(公告)号：US20160134820A1
公开(公告)日：2016-05-12
申请号：US14536733
申请日：2014-11-10
Applicant: RAYTHEON COMPANY
Inventor： Bryan W. Kean , John L. Vampola
IPC: H04N5/355 , H04N5/3745
CPC classification number: H04N5/3559 , H04N5/3745 , H04N5/37452
Abstract: According to one aspect, embodiments herein provide a unit cell comprising a photodiode, a MOSCap having an input node coupled to the photodiode, a reset switch selectively coupled between the MOSCap and a reset voltage, and a transistor coupled to the input node of the MOSCap, wherein, in a first mode of operation of the unit cell, the reset switch is configured in an open state and charge generated by light incident on the photodiode accumulates at the input node of the MOSCap in response to voltage at the input node being less than a threshold voltage, and wherein, in a second mode of operation of the unit cell, the reset switch is configured in the open state and the charge generated by the light incident on the photodiode accumulates on the MOSCap in response to the voltage at the input node being greater than the threshold voltage.
Abstract translation: 根据一个方面，本文的实施例提供了一种单元单元，其包括光电二极管，具有耦合到光电二极管的输入节点的MOSCap，选择性地耦合在MOSCap和复位电压之间的复位开关以及耦合到MOSCap的输入节点的晶体管 ，其中在所述单电池的第一操作模式中，所述复位开关被配置为处于断开状态，并且响应于所述输入节点处的电压而在所述MOSCap的输入节点处累积的入射到所述光电二极管上的光产生的电荷累积 并且其中，在所述单位电池的第二工作模式中，所述复位开关被配置为处于打开状态，并且由入射到所述光电二极管上的光产生的电荷响应于所述MOSCap处的电压积累在所述MOSCap上 输入节点大于阈值电压。
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5.发明申请公开(公告)号：US20150215536A1
公开(公告)日：2015-07-30
申请号：US14167194
申请日：2014-01-29
Applicant: RAYTHEON COMPANY
Inventor： David Buell , John L. Vampola , Micky R. Harris , Steven Botts
CPC classification number: H04N5/23245 , H04N5/2257 , H04N5/2259 , H04N5/257 , H04N5/33 , H04N5/378 , H04N9/09 , H04N9/10 , H04N2201/0452 , H04N2201/0458 , H04N2209/048
Abstract: A combined scanning and staring (SCARING) focal plane array (FPA) imaging system having a plurality of modes of operation is provided. In one example, the SCARING FPA system includes a photodetector array with a plurality of photodetectors arranged in a plurality of photodetector rows, a readout integrated circuit (ROIC) coupled to the photodetector array, and a processor coupled to the ROIC. The processor coupled to the ROIC is configured to dynamically configure the SCARING FPA between a scanning mode of operation and a staring mode of operation.
Abstract translation: 提供具有多种操作模式的组合扫描和盯着（SCARING）焦平面阵列（FPA）成像系统。 在一个示例中，SCARING FPA系统包括具有布置在多个光电检测器行中的多个光电检测器的光电检测器阵列，耦合到光电检测器阵列的读出集成电路（ROIC）和耦合到ROIC的处理器。 耦合到ROIC的处理器被配置为在扫描操作模式和盯着操作模式之间动态地配置SCARING FPA。
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Patent Agency Ranking
公开(公告)号：US11710756B2
公开(公告)日：2023-07-25
申请号：US16952783
申请日：2020-11-19
Applicant: RAYTHEON COMPANY
Inventor： Jamal I. Mustafa , Robert C. Anderson , John L. Vampola , Sean P. Kilcoyne , Eric R. Miller , George Grama
IPC: H01L27/146
CPC classification number: H01L27/14634 , H01L27/1469 , H01L27/14621 , H01L27/14625 , H01L27/14685 , H01L27/14687 , H01L27/1462
Abstract: A direct-bond hybridization (DBH) method is provided to assemble a sensor wafer device. The DBH method includes fabricating an optical element on a handle wafer and depositing first oxide with n-x thickness on the optical element where n is an expected final oxide thickness of the sensor wafer, depositing second oxide with x thickness onto a sensor wafer, executing layer transfer of the optical element by a DBH fusion bond technique to the sensor wafer whereby the first and second oxides form an oxide layer of n thickness between the optical element and the sensor wafer and removing the handle wafer.
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7.发明授权公开(公告)号：US11356622B1
公开(公告)日：2022-06-07
申请号：US17214751
申请日：2021-03-26
Applicant: RAYTHEON COMPANY
Inventor： Bryan W. Kean , John L. Vampola , Joshua J. Cantrell
IPC: H04N5/353 , H04N5/374 , H04N5/378 , H03F3/08 , H03F3/45 , H03F1/00 , H03F1/02 , H03F1/22 , H04N5/3745
Abstract: An image capturing device is provided, which includes a capacitive trans-impedance amplifier (CTIA) unit cell. The CTIA unit cell includes an image detector and a switching network. The image detector is configured to detect light having a first color and light having a second color different from the first color, and to generate a photocurrent in response to detecting the light. The switching network includes a CTIA switch, a CTIA low reset switch, and a CTIA high-reset biasing switch. The CTIA switch sets a first reset level of the CTIA unit cell to a first voltage in response invoking a first switching state of the CTIA low-reset switch and sets a second reset level of the CTIA to a second voltage greater than the first voltage level in response to invoking a second switching state of the CTIA low-reset switch.
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公开(公告)号：US10672826B2
公开(公告)日：2020-06-02
申请号：US15955820
申请日：2018-04-18
Applicant: RAYTHEON COMPANY
Inventor： Sean P. Kilcoyne , John L. Vampola , George Paloczi
IPC: H01L27/146 , H04N5/335 , H04N5/235
Abstract: An imaging system includes a focal plane array comprising a first row of photodetectors, a second row of photodetectors adjacent to the first row of photodetectors, and a segmented isolation grid including portions disposed between photodetectors in the first row of photodetectors and photodetectors in the second row of photodetectors.
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公开(公告)号：US10418406B2
公开(公告)日：2019-09-17
申请号：US15856747
申请日：2017-12-28
Applicant: RAYTHEON COMPANY
Inventor： Sean P. Kilcoyne , John L. Vampola , Barry M. Starr , Chad W. Fulk , Christopher L. Mears , John J. Drab
IPC: H01L27/146 , H01L21/768 , H01L21/302
Abstract: Aspects and examples described herein provide a hybrid imaging sensor chip assembly for reducing undesired radiative transfer between a complementary metal-oxide semiconductor (CMOS) read-out integrated circuit (ROIC) and an optical detector, and methods of manufacturing a hybrid imaging sensor chip assembly. In one example, a hybrid imaging sensor chip assembly includes an optical detector configured to collect electromagnetic radiation incident thereon, a complementary metal-oxide semiconductor (CMOS) read-out integrated circuit (ROIC), and a radiation-shielding wafer interposed between the optical detector and the CMOS ROIC, the radiation-shielding wafer including a plurality of through wafer vias (TWVs) electrically coupled to the optical detector and the CMOS ROIC, the radiation-shielding wafer being positioned to prevent radiative transfer between the CMOS ROIC and the optical detector.
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公开(公告)号：US20160331265A1
公开(公告)日：2016-11-17
申请号：US14711042
申请日：2015-05-13
Applicant: Raytheon Company
Inventor： Matthew D. Chambers , John L. Vampola , Micky Harris
IPC: A61B5/05
CPC classification number: A61B5/05 , A61B5/7203 , A61B2562/046 , A61B2576/00 , H01L27/14856 , H04N5/347 , H04N5/37206 , H04N5/3743
Abstract: A system including a detector array configured to receive electromagnetic (EM) radiation from a target object, the detector array having one or more detectors is disclosed. The system also includes a readout integrated circuit and one or more processors. The readout integrated circuit has a circuit comprising a number of detector boundary selection components, each one of the number of detector boundary selection components configured to select or adjust a detector boundary from least one of a sub-column boundary or an adjustable boundary.
Abstract translation: 一种包括被配置为从目标物体接收电磁（EM）辐射的检测器阵列的系统，所述检测器阵列具有一个或多个检测器。 该系统还包括读出集成电路和一个或多个处理器。 读出集成电路具有包括多个检测器边界选择部件的电路，每个检测器边界选择部件中的每一个被配置为从子列边界或可调边界中的至少一个选择或调整检测器边界。
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