公开(公告)号：US20190067472A1

公开(公告)日：2019-02-28

申请号：US16036434

申请日：2018-07-16

Applicant: Renesas Electronics Corporation

Inventor： Makoto KOSHIMIZU ,  Komaki INDUE ,  Hideki NIWAYAMA

IPC: H01L29/78 ,  H01L29/08 ,  H01L29/10 ,  H01L29/423 ,  H01L29/66 ,  H01L21/266 ,  H01L29/36 ,  H01L21/265 ,  H01L27/088 ,  H01L21/8234 ,  H01L27/02 ,  H01L29/06

Abstract: A semiconductor device with improved performance. A channel region and a well region having a lower impurity concentration than the channel region are formed in a semiconductor substrate on the source region side of an LDMOS. The channel region partially overlaps a gate electrode in plan view. In the gate length direction of the LDMOS, an end of the well region in the channel region is at a distance from the end of the gate electrode on the source region side of the LDMOS in a manner to be away from the gate electrode.

公开(公告)号：US20240162221A1

公开(公告)日：2024-05-16

申请号：US18471662

申请日：2023-09-21

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Hiroyoshi KUDOU ,  Hideki NIWAYAMA

IPC: H01L27/06 ,  H01L21/02 ,  H01L21/265 ,  H01L21/266 ,  H01L21/8234 ,  H01L29/06 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L27/0629 ,  H01L21/02244 ,  H01L21/02255 ,  H01L21/26513 ,  H01L21/266 ,  H01L21/82345 ,  H01L21/823475 ,  H01L21/823481 ,  H01L21/823493 ,  H01L28/20 ,  H01L29/063 ,  H01L29/66734 ,  H01L29/7802 ,  H01L29/7813

Abstract: Reliability of a semiconductor device is improved, and a decrease in yield is suppressed. A hard mask is formed on an upper surface of a semiconductor substrate. A trench is formed in the semiconductor substrate exposed out from the hard mask. A gate insulating film is formed in the trench. A conductive film is formed on the gate insulating film and the hard mask. The conductive film on the hard mask is removed, and a gate electrode is formed in the trench. A cap film is formed on an upper surface of the gate electrode. The hard mask is removed. A gate insulating film is formed on the upper surface of the semiconductor substrate. A conductive film is formed on the gate insulating film and the cap film. The conductive film on the cap film is removed, and a gate electrode is formed on the gate insulating film.

公开(公告)号：US20190189737A1

公开(公告)日：2019-06-20

申请号：US16275469

申请日：2019-02-14

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Makoto KOSHIMIZU ,  Hideki NIWAYAMA ,  Kazuyuki UMEZU ,  Hiroki SOEDA ,  Atsushi TACHIGAMI ,  Takeshi IIJIMA

IPC: H01L29/06 ,  H01L21/762 ,  H01L21/8238 ,  H01L29/78 ,  H01L29/66 ,  H01L27/092 ,  H01L29/423

CPC classification number: H01L29/0649 ,  H01L21/76205 ,  H01L21/76224 ,  H01L21/82385 ,  H01L21/823857 ,  H01L21/823878 ,  H01L27/0922 ,  H01L29/0638 ,  H01L29/0653 ,  H01L29/0661 ,  H01L29/0696 ,  H01L29/086 ,  H01L29/0878 ,  H01L29/1083 ,  H01L29/41758 ,  H01L29/42368 ,  H01L29/4238 ,  H01L29/456 ,  H01L29/4933 ,  H01L29/665 ,  H01L29/66659 ,  H01L29/66689 ,  H01L29/7816 ,  H01L29/7835

Abstract: A terrace insulating film (SL) to be overridden by a gate electrode (G) of an nLDMOS device is configured by LOCOS, and a device isolation portion (SS) is configured by STI. Furthermore, on an outermost periphery of an active region where a plurality of nLDMOS devices are formed, a guard ring having the same potential as that of a drain region (D) is provided. And, via this guard ring, the device isolation portion (SS) is formed in a periphery of the active region, thereby not connecting but isolating the terrace insulating film (SL) and the device isolation portion (SS) from each other.

公开(公告)号：US20240162222A1

公开(公告)日：2024-05-16

申请号：US18509870

申请日：2023-11-15

Applicant: Renesas Electronics Corporation

Inventor： Hiroshi YANAGIGAWA ,  Hideki NIWAYAMA ,  Hiroyoshi KUDOU ,  Kazuhisa MORI ,  Kodai WADA

IPC: H01L27/06 ,  H01L21/8238 ,  H01L29/06 ,  H01L29/10 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L27/0629 ,  H01L21/823814 ,  H01L21/823828 ,  H01L21/823878 ,  H01L21/823885 ,  H01L21/823892 ,  H01L28/20 ,  H01L29/063 ,  H01L29/0653 ,  H01L29/1095 ,  H01L29/66734 ,  H01L29/7813

Abstract: Reliability of a semiconductor device is improved and reduction in yield is reduced. In a semiconductor substrate SUB, a trench TR is formed. A gate-electrode GE1 is formed inside the trench TR via a gate insulating film GI1. In the semiconductor substrate SUB, a body region PB, a well region PW1 and a well region NW1 are formed. A source-region NS is formed in the body-region PB. In the well region PW1, an n-type source region and an n-type drain region are formed. In the well region NW1, a p-type source region and a p-type drain region are formed. The source region NS, the n-type source region, the n-type drain region, the p-type source region and the p-type drain region are subjected to heat treatment. After heat treatment, a p-type column region PC is formed in the semiconductor substrate SUB located below the body region PB.

公开(公告)号：US20240162143A1

公开(公告)日：2024-05-16

申请号：US18509874

申请日：2023-11-15

Applicant: Renesas Electronics Corporation

Inventor： Hiroshi YANAGIGAWA ,  Hideki NIWAYAMA ,  Hiroyoshi KUDOU ,  Kazuhisa MORI ,  Kodai WADA

IPC: H01L23/522 ,  H01L21/768 ,  H01L27/088 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L23/5226 ,  H01L21/76802 ,  H01L21/76837 ,  H01L21/76877 ,  H01L21/76885 ,  H01L27/088 ,  H01L29/66734 ,  H01L29/7813

Abstract: In a semiconductor substrate SUB, a trench TR is formed.
A gate-electrode GE1 is formed inside the trench TR via a gate insulating film GI1. A body region PB, a well region PW1 and a well region NW1 are formed. A source-region NS is formed in the body-region PB. In the well region PW1, an n-type source region and an n-type drain region are formed. In the well region NW1, a p-type source region and a p-type drain region are formed. An interlayer insulating film IL1 is formed on the upper surface of semiconductor substrate SUB. In the interlayer insulating film IL1, a hole CH1 is formed in the source region NS and in the body region PB. Holes CH3 are formed in the interlayer insulating film IL1 so as to reach the n-type source region, the n-type drain region, the p-type source region and the p-type drain region.

公开(公告)号：US20200212176A1

公开(公告)日：2020-07-02

申请号：US16815636

申请日：2020-03-11

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Makoto KOSHIMIZU ,  Hideki NIWAYAMA ,  Kazuyuki UMEZU ,  Hiroki SOEDA ,  Atsushi TACHIGAMI ,  Takeshi IIJIMA

IPC: H01L29/06 ,  H01L21/762 ,  H01L29/78 ,  H01L29/66 ,  H01L29/423 ,  H01L27/092 ,  H01L21/8238

Abstract: A terrace insulating film (SL) to be overridden by a gate electrode (G) of an nLDMOS device is configured by LOCOS, and a device isolation portion (SS) is configured by STI. Furthermore, on an outermost periphery of an active region where a plurality of nLDMOS devices are formed, a guard ring having the same potential as that of a drain region (D) is provided. And, via this guard ring, the device isolation portion (SS) is formed in a periphery of the active region, thereby not connecting but isolating the terrace insulating film (SL) and the device isolation portion (SS) from each other.