公开(公告)号：US20210233841A1

公开(公告)日：2021-07-29

申请号：US16752925

申请日：2020-01-27

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Shunji KUBO ,  Kazuki NIINO ,  Hajime HAYASHIMOTO

IPC: H01L23/522 ,  H01L23/528

Abstract: A semiconductor device includes a semiconductor substrate, a semiconductor layer, an insulating film, a conductive film, a first electrode pad, a second electrode pad, and a third electrode pad. The semiconductor layer includes a first semiconductor region having a first conductivity type and a second semiconductor region having a second conductivity type opposite to the first conductivity type. The insulating film is formed on the semiconductor layer. The conductive film is formed on the second semiconductor region through the insulating film interposed therebetween. The first electrode pad is configured to be electrically connected with the first semiconductor region and is configured to be electrically connected with the power supply circuit. The second electrode pad is configured to be electrically connected with the second semiconductor region and is configured to allow a signal to be provided toward an external circuit through the second electrode pad.

公开(公告)号：US20160064559A1

公开(公告)日：2016-03-03

申请号：US14835373

申请日：2015-08-25

Applicant: Renesas Electronics Corporation

Inventor： Mikio TSUJIUCHI ,  Kouji TANAKA ,  Yasuki YOSHIHISA ,  Shunji KUBO

IPC: H01L29/78 ,  H01L29/66 ,  H01L29/40 ,  H01L29/08 ,  H01L29/06

CPC classification number: H01L29/7835 ,  H01L21/26586 ,  H01L21/76224 ,  H01L29/0653 ,  H01L29/0847 ,  H01L29/0873 ,  H01L29/1083 ,  H01L29/1087 ,  H01L29/404 ,  H01L29/407 ,  H01L29/4175 ,  H01L29/66659 ,  H01L29/66689 ,  H01L29/7816

Abstract: A semiconductor substrate has a main surface with an n type offset region having a trench portion formed of a plurality of trenches extending in a direction from an n+ drain region toward an n+ source region. The plurality of trenches each have a conducting layer therein extending in the main surface in the direction from the n+ drain region toward the n+ source region.

Abstract translation: 半导体衬底具有主表面，其具有n型偏移区域，其具有由沿从n +漏极区域朝向n +源极区域的方向延伸的多个沟槽形成的沟槽部分。 多个沟槽中的导电层各自在从n +漏极区域向n +源极区域的方向上在主表面上延伸。

公开(公告)号：US20210167012A1

公开(公告)日：2021-06-03

申请号：US16700485

申请日：2019-12-02

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Shunji KUBO ,  Koichi ANDO ,  Eiji IO ,  Hideyuki TAJIMA ,  Tetsuya IIDA

IPC: H01L23/522 ,  H01L23/373

Abstract: A semiconductor device includes a base member, a multilayer wiring layer, and a first resistive element. The multilayer wiring layer is formed on the base member. The first resistive element is formed in the multilayer wiring layer. The first resistive element includes a first conductive part, a second conductive part and a third conductive part. The second conductive part is formed over the first conductive part. The third conductive part electrically connects the first conductive part and the second conductive part with each other. A length of the third conductive part in a first direction along a surface of the base member is greater than a length of the third conductive part in a second direction along the surface of the base member and perpendicular to the first direction.

公开(公告)号：US20150115360A1

公开(公告)日：2015-04-30

申请号：US14594034

申请日：2015-01-09

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Shunji KUBO

IPC: H01L29/78 ,  H01L29/10 ,  H01L29/06

CPC classification number: H01L29/0847 ,  H01L29/0615 ,  H01L29/0653 ,  H01L29/0692 ,  H01L29/0696 ,  H01L29/086 ,  H01L29/0865 ,  H01L29/0878 ,  H01L29/1045 ,  H01L29/1095 ,  H01L29/42368 ,  H01L29/4238 ,  H01L29/66659 ,  H01L29/66689 ,  H01L29/7816 ,  H01L29/7835

Abstract: An N type well (NW) is formed over a prescribed depth from a main surface of a semiconductor substrate (SUB), and a P type well (PW) and an N type drain region (ND) are formed in the N type well (NW). An N type source region (NS), an N+ type source region (NNS), and a P+ type impurity region (BCR) are formed in the P type well (PW). The N type source region (NS) is formed on a region situated directly below the N+ type source region (NNS), and not on a region situated directly below the P+ type impurity region (BCR), and the P+ type impurity region (BCR) is in direct contact with the P type well (PW).

Abstract translation: 在半导体衬底（SUB）的主表面上形成规定深度的N型阱（NW），在N型阱中形成P型阱（PW）和N型漏极区域（ND） NW）。 在P型阱（PW）中形成N型源极区（NS），N +型源极区（NNS）和P +型杂质区（BCR）。 N型源极区（NS）形成在位于N +型源极区域（NNS）正下方的区域上，而不是位于位于P +型杂质区域（BCR）正下方的区域上，并且P +型杂质区域 ）与P型阱（PW）直接接触。

公开(公告)号：US20140252441A1

公开(公告)日：2014-09-11

申请号：US14287862

申请日：2014-05-27

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Atsushi HACHISUKA ,  Atsushi AMO ,  Tatsuo KASAOKA ,  Shunji KUBO

IPC: H01L27/108

CPC classification number: H01L27/10829 ,  H01L21/76807 ,  H01L21/76808 ,  H01L21/76838 ,  H01L21/76877 ,  H01L23/485 ,  H01L27/10811 ,  H01L27/10885 ,  H01L27/10888 ,  H01L27/10894 ,  H01L27/10897 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A technique for enhancing the performance of a memory- and logic-equipped semiconductor device is provided. The semiconductor device comprises a semiconductor substrate, and insulating layer on the semiconductor substrate, a plurality of contact plugs in the insulating layer, and an insulating layer where capacitors, a plurality of contact plugs, barrier metal layers and copper interconnections are formed. Source/drain regions in the upper surface of the semiconductor substrate are electrically connected to the copper interconnections. One of adjacent source/drain regions in the upper surface of the semiconductor substrate is electrically connected to the copper interconnection, while the other is electrically connected to the capacitor.

Abstract translation: 提供了一种用于提高存储器和逻辑器件的半导体器件的性能的技术。 半导体器件包括半导体衬底和半导体衬底上的绝缘层，绝缘层中的多个接触插塞以及形成电容器，多个接触插塞，阻挡金属层和铜互连的绝缘层。 半导体衬底的上表面中的源/漏区电连接到铜互连。 在半导体衬底的上表面中的相邻源极/漏极区域中的一个电连接到铜互连，而另一个电连接到电容器。