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    Three-level digital-to-analog converter
    1.
    发明授权
    Three-level digital-to-analog converter 有权
    三电平数模转换器

    公开(公告)号：US08456341B2

    公开(公告)日：2013-06-04

    申请号：US13134301

    申请日：2011-06-03

    申请人： Rahmi Hezar ,  Baher Haroun ,  Halil Kiper ,  Mounir Fares ,  Ajay Kumar

    发明人： Rahmi Hezar ,  Baher Haroun ,  Halil Kiper ,  Mounir Fares ,  Ajay Kumar

    IPC分类号： H03M1/66

    CPC分类号： H03M1/66 ,  H03M1/747 ,  H03M3/464

    摘要： A system for processing a signal includes a detector configured to detect a two-level stream of bits; a converter configured to generate a three-level control signal based on two adjacent values within the two-level stream of bits; and a switch configured to determine which of three different paths to couple a current source to based on a value of the three-level control signal. Thus, based on adjacent values of the output stream a three-level control signal is generated which controls coupling of the current source to one of three different paths. This type of three-level digital-to-analog converter can be, for example, part of the feedback loop of an analog-to-digital converter. Similar techniques can also be utilized in a multi-segment digital-to-analog converter in which each segment of the DAC is controlled by a 3-level control signal and the DAC is implement using PMOS devices. The current source for each DAC segment is diverted to ground, the M-node, or the P-node depending on the value of the 3-level control signal.

    摘要翻译： 一种用于处理信号的系统包括：检测器，被配置为检测两级比特流; 转换器，被配置为基于所述两级比特流内的两个相邻值生成三电平控制信号; 以及开关，被配置为基于三电平控制信号的值来确定三个不同路径中的哪一个耦合电流源。 因此，基于输出流的相邻值，生成三电平控制信号，其控制电流源与三个不同路径之一的耦合。 这种类型的三电平数模转换器可以是例如模数转换器的反馈回路的一部分。 类似技术也可以用在多段数模转换器中，其中DAC的每个段由3电平控制信号控制，并且使用PMOS器件来实现DAC。 每个DAC段的电流源根据3电平控制信号的值转移到地，M节点或P节点。

    Three-level digital-to-analog converter
    2.
    发明申请
    Three-level digital-to-analog converter 有权
    三电平数模转换器

    公开(公告)号：US20120306678A1

    公开(公告)日：2012-12-06

    申请号：US13134301

    申请日：2011-06-03

    申请人： Rahmi Hezar ,  Baher Haroun ,  Halil Kiper ,  Mounir Fares ,  Ajay Kumar

    发明人： Rahmi Hezar ,  Baher Haroun ,  Halil Kiper ,  Mounir Fares ,  Ajay Kumar

    IPC分类号： H03M1/72

    CPC分类号： H03M1/66 ,  H03M1/747 ,  H03M3/464

    摘要： A system for processing a signal includes a detector configured to detect a two-level stream of bits; a converter configured to generate a three-level control signal based on two adjacent values within the two-level stream of bits; and a switch configured to determine which of three different paths to couple a current source to based on a value of the three-level control signal. Thus, based on adjacent values of the output stream a three-level control signal is generated which controls coupling of the current source to one of three different paths. This type of three-level digital-to-analog converter can be, for example, part of the feedback loop of an analog-to-digital converter. Similar techniques can also be utilized in a multi-segment digital-to-analog converter in which each segment of the DAC is controlled by a 3-level control signal and the DAC is implement using PMOS devices. The current source for each DAC segment is diverted to ground, the M-node, or the P-node depending on the value of the 3-level control signal.

    摘要翻译： 一种用于处理信号的系统包括：检测器，被配置为检测两级比特流; 转换器，被配置为基于所述两级比特流内的两个相邻值生成三电平控制信号; 以及开关，被配置为基于三电平控制信号的值来确定三个不同路径中的哪一个耦合电流源。 因此，基于输出流的相邻值，生成三电平控制信号，其控制电流源与三个不同路径之一的耦合。 这种类型的三电平数模转换器可以是例如模数转换器的反馈回路的一部分。 类似的技术也可以用在多段数模转换器中，其中DAC的每个段由3电平控制信号控制，并且使用PMOS器件实现DAC。 每个DAC段的电流源根据3电平控制信号的值转移到地，M节点或P节点。

    UV-CURE PRE-TREATMENT OF CARRIER FILM FOR WAFER DICING USING HYBRID LASER SCRIBING AND PLASMA ETCH APPROACH
    7.
    发明申请
    UV-CURE PRE-TREATMENT OF CARRIER FILM FOR WAFER DICING USING HYBRID LASER SCRIBING AND PLASMA ETCH APPROACH 有权
    使用混合激光扫描和等离子体蚀刻方法进行波长涂覆的载体膜的UV固化预处理

    公开(公告)号：US20160315009A1

    公开(公告)日：2016-10-27

    申请号：US14697391

    申请日：2015-04-27

    申请人： Wei-Sheng Lei ,  Brad Eaton ,  Jungrae Park ,  Ajay Kumar ,  James S. Papanu ,  Prabhat Kumar

    发明人： Wei-Sheng Lei ,  Brad Eaton ,  Jungrae Park ,  Ajay Kumar ,  James S. Papanu ,  Prabhat Kumar

    IPC分类号： H01L21/78 ,  H01L21/683 ,  H01L21/268 ,  H01L21/67 ,  H01L21/308 ,  H01L21/3065

    CPC分类号： H01L21/78 ,  H01L21/268 ,  H01L21/3065 ,  H01L21/3086 ,  H01L21/67069 ,  H01L21/67207 ,  H01L21/6836 ,  H01L2221/68327 ,  H01L2221/6834 ,  H01L2221/68381

    摘要： Methods of dicing semiconductor wafers, each wafer having a plurality of integrated circuits, are described. In an example, a method of dicing a semiconductor wafer having a plurality of integrated circuits on a front side of the semiconductor wafer includes adhering a back side the semiconductor wafer on the dicing tape of a substrate carrier. Subsequent to adhering the semiconductor wafer on a dicing tape, the dicing tape is treated with a UV-cure process. Subsequent to treating the dicing tape with the UV-cure process, a dicing mask is formed on the front side of the semiconductor wafer, the dicing mask covering and protecting the integrated circuits. The dicing mask is patterned with a laser scribing process to provide gaps in the dicing mask, the gaps exposing regions of the semiconductor wafer between the integrated circuits. The semiconductor wafer is plasma etched through the gaps in the dicing mask layer to singulate the integrated circuits.

    摘要翻译： 对具有多个集成电路的每个晶片进行切割的半导体晶片的方法进行了说明。 在一个示例中，在半导体晶片的正面上切割具有多个集成电路的半导体晶片的方法包括将半导体晶片的背面粘附在基板载体的切割带上。 在将半导体晶片粘附在切割带上之后，用UV固化工艺处理切割带。 在通过UV固化处理处理切割带之后，在半导体晶片的前侧形成切割掩模，该切割掩模覆盖并保护集成电路。 用激光刻划工艺对切割掩模进行图案化，以在切割掩模之间提供间隙，在半导体晶片的间隙暴露在集成电路之间。 通过切割掩模层中的间隙对半导体晶片进行等离子体蚀刻，以对集成电路进行分离。

    PROXIMITY CONTACT COVER RING FOR PLASMA DICING
    8.
    发明申请
    PROXIMITY CONTACT COVER RING FOR PLASMA DICING 审中-公开
    用于等离子体定位的接头盖

    公开(公告)号：US20160086852A1

    公开(公告)日：2016-03-24

    申请号：US14491856

    申请日：2014-09-19

    申请人： James M. Holden ,  Alexander N. Lerner ,  Ajay Kumar ,  Aparna Iyer ,  Alan Hiroshi Ouye

    发明人： James M. Holden ,  Alexander N. Lerner ,  Ajay Kumar ,  Aparna Iyer ,  Alan Hiroshi Ouye

    IPC分类号： H01L21/78 ,  H01J37/32 ,  H01L21/67 ,  H01L21/683 ,  H01L21/3065 ,  H01L21/308

    摘要： Methods of and carriers for dicing semiconductor wafers, each wafer having a plurality of integrated circuits, are described. In an example, a cover ring for protecting a carrier and substrate assembly during an etch process includes an inner opening having a diameter smaller than the diameter of a substrate of the carrier and substrate assembly. An outer frame surrounds the inner opening. The outer frame has a bevel for accommodating an outermost portion of the substrate of the carrier and substrate assembly.

    摘要翻译： 描述了半导体晶片切割的方法和载体，每个晶片具有多个集成电路。 在一个示例中，用于在蚀刻工艺期间保护载体和基底组件的盖环包括直径小于载体和基底组件的基底的直径的内部开口。 外框围绕内开口。 外框架具有用于容纳载体和基底组件的基底的最外部分的斜面。

    DICING TAPE PROTECTION FOR WAFER DICING USING LASER SCRIBE PROCESS
    10.
    发明申请
    DICING TAPE PROTECTION FOR WAFER DICING USING LASER SCRIBE PROCESS 有权
    使用激光扫描工艺制造的波纹贴片保护

    公开(公告)号：US20150311118A1

    公开(公告)日：2015-10-29

    申请号：US14272101

    申请日：2014-05-07

    申请人： Wei-Sheng Lei ,  Brad Eaton ,  Ajay Kumar

    发明人： Wei-Sheng Lei ,  Brad Eaton ,  Ajay Kumar

    IPC分类号： H01L21/78 ,  H01L21/683

    CPC分类号： H01L21/78 ,  H01L21/67092 ,  H01L21/6836 ,  H01L2221/68327 ,  H01L2221/68377

    摘要： Methods of and apparatuses for dicing semiconductor wafers, each wafer having a plurality of integrated circuits, are described. In an example, a method of scribing a semiconductor wafer having a plurality of integrated circuits involves adhering a backside of a semiconductor wafer to an inner portion of a carrier tape of a substrate carrier that includes a tape frame mounted above the carrier tape. The method also involves overlaying a protective frame above a front side of the semiconductor wafer and above an exposed outer portion of the carrier tape, the protective frame having an opening exposing an inner region of the front side of the semiconductor wafer. The method also involves laser scribing the front side of the semiconductor wafer with the protective frame in place.

    摘要翻译： 对具有多个集成电路的各晶片的切割半导体晶片的方法和装置进行说明。 在一个示例中，划片具有多个集成电路的半导体晶片的方法包括将半导体晶片的背面粘附到包括安装在载带上方的带框架的基板载体的载带的内部。 该方法还包括将保护框架覆盖在半导体晶片的前侧上方并且在载带的暴露的外部部分上方，保护框架具有暴露半导体晶片的前侧的内部区域的开口。 该方法还包括用保护框架将半导体晶片的前侧激光划片就位。