公开(公告)号：US10026666B2

公开(公告)日：2018-07-17

申请号：US14513871

申请日：2014-10-14

Applicant: Rambus Inc.

Inventor： Nitin Juneja ,  Wendemagegnehu Beyene ,  David A. Secker ,  Ely K. Tsern

IPC: H01L23/48 ,  H01L23/52 ,  H01L29/40 ,  H01L23/13 ,  H01L25/065 ,  H01L23/498 ,  H01L25/18 ,  H01L23/00

Abstract: Disclosed is a package-on-package (PoP) assembly comprises a two-tiered windowed ball grid array (BGA) and a system on a chip (SoC) package. Window openings in the two tiers of the BGA are of different sizes to allow for wirebond landing pads on the first tier. A DRAM die is mounted to the BGA flipped over (i.e., wirebond pads facing the BGA package.) The DRAM die is wirebonded through the window in the BGA. For multi-channel systems and higher memory capacity, the DRAM die will have low-cost through-silicon vias (TSVs) that connect to stacked DRAM die(s). The stacked DRAM dies may be offset or rotated to align active TSVs with passive TSVs thereby enabling unique connections to certain DRAM dies in the stack.

公开(公告)号：US12087681B2

公开(公告)日：2024-09-10

申请号：US18218280

申请日：2023-07-05

Applicant: Rambus Inc.

Inventor： Shahram Nikoukary ,  Jonghyun Cho ,  Nitin Juneja ,  Ming Li

IPC: H01L23/498

CPC classification number: H01L23/49838 ,  H01L23/49816

Abstract: Disclosed is an integrated circuit die of a memory buffer integrated circuit that is placed aggregately closer to the solder balls that connect to the input (i.e., host command/address—C/A) signals than the output solder balls (i.e., memory device C/A) signals. This decreases the length of the host C/A signals from the memory controller to the memory buffer device when the memory module is placed in a system.

公开(公告)号：US11742277B2

公开(公告)日：2023-08-29

申请号：US17264231

申请日：2019-08-12

Applicant: Rambus Inc.

Inventor： Shahram Nikoukary ,  Jonghyun Cho ,  Nitin Juneja ,  Ming Li

IPC: H01L23/498

CPC classification number: H01L23/49838 ,  H01L23/49816

Abstract: Disclosed is an integrated circuit die of a memory buffer integrated circuit that is placed aggregately closer to the solder balls that connect to the input (i.e., host command/address—C/A) signals than the output solder balls (i.e., memory device C/A) signals. This decreases the length of the host C/A signals from the memory controller to the memory buffer device when the memory module is placed in a system.

公开(公告)号：US20150108656A1

公开(公告)日：2015-04-23

申请号：US14513871

申请日：2014-10-14

Applicant: Rambus Inc.

Inventor： Nitin Juneja ,  Wendemagegnehu Beyene ,  David A. Secker ,  Ely K. Tsern

IPC: H01L23/498 ,  H01L25/10 ,  H01L23/00

CPC classification number: H01L23/13 ,  H01L23/481 ,  H01L23/49816 ,  H01L23/49833 ,  H01L24/05 ,  H01L24/06 ,  H01L24/16 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L25/0657 ,  H01L25/18 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/05548 ,  H01L2224/05552 ,  H01L2224/0557 ,  H01L2224/05571 ,  H01L2224/06181 ,  H01L2224/13025 ,  H01L2224/131 ,  H01L2224/16146 ,  H01L2224/17181 ,  H01L2224/48091 ,  H01L2224/4824 ,  H01L2224/49 ,  H01L2224/73257 ,  H01L2225/0651 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/0652 ,  H01L2225/06544 ,  H01L2225/06572 ,  H01L2924/00014 ,  H01L2924/1436 ,  H01L2924/1517 ,  H01L2924/15311 ,  H01L2224/45099 ,  H01L2224/05599 ,  H01L2924/00012 ,  H01L2924/014

Abstract: Disclosed is a package-on-package (PoP) assembly comprises a two-tiered windowed ball grid array (BGA) and a system on a chip (SoC) package. Window openings in the two tiers of the BGA are of different sizes to allow for wirebond landing pads on the first tier. A DRAM die is mounted to the BGA flipped over (i.e., wirebond pads facing the BGA package.) The DRAM die is wirebonded through the window in the BGA. For multi-channel systems and higher memory capacity, the DRAM die will have low-cost through-silicon vias (TSVs) that connect to stacked DRAM die(s). The stacked DRAM dies may be offset or rotated to align active TSVs with passive TSVs thereby enabling unique connections to certain DRAM dies in the stack.

Abstract translation: 公开了一种封装封装（PoP）组件，其包括双层窗口球栅阵列（BGA）和片上系统（SoC）封装。 BGA两层的窗口开口尺寸不同，可以在第一层上使用引线键盘。 DRAM裸片安装到BGA翻转（即，面向BGA封装的引线焊盘）。DRAM裸片通过BGA中的窗口进行引线键合。 对于多通道系统和更高的存储容量，DRAM裸片将具有连接到堆叠的DRAM裸片的低成本的硅通孔（TSV）。 堆叠的DRAM裸片可以偏移或旋转以使有源TSV与无源TSV对准，从而实现与堆叠中的某些DRAM裸片的唯一连接。