公开(公告)号：US20150372151A1

公开(公告)日：2015-12-24

申请号：US14839586

申请日：2015-08-28

Applicant: Renesas Electronics Corporation

Inventor： Itaru YANAGI ,  Toshiyuki MINE ,  Hirotaka HAMAMURA ,  Digh HISAMOTO ,  Yasuhiro SHIMAMOTO

IPC: H01L29/792 ,  H01L29/51

CPC classification number: H01L29/792 ,  G11C16/0466 ,  H01L21/28273 ,  H01L21/28282 ,  H01L27/105 ,  H01L27/115 ,  H01L27/11521 ,  H01L27/11526 ,  H01L27/11568 ,  H01L27/11573 ,  H01L29/42344 ,  H01L29/513

Abstract: In a non-volatile memory in which writing/erasing is performed by changing a total charge amount by injecting electrons and holes into a silicon nitride film serving as a charge accumulation layer, in order to realize a high efficiency of a hole injection from a gate electrode, the gate electrode of a memory cell comprises a laminated structure made of a plurality of polysilicon films with different impurity concentrations, for example, a two-layered structure comprising a p-type polysilicon film with a low impurity concentration and a p′-type polysilicon film with a high impurity concentration deposited thereon.

Abstract translation: 在通过将电子和空穴注入到用作电荷累积层的氮化硅膜中来改变总电荷量进行写/擦除的非易失性存储器中，为了实现从栅极的空穴注入的高效率 电极，存储单元的栅电极包括由具有不同杂质浓度的多个多晶硅膜制成的叠层结构，例如包括具有低杂质浓度的p型多晶硅膜和二进制型 沉积有高杂质浓度的多晶硅膜。

公开(公告)号：US20140327066A1

公开(公告)日：2014-11-06

申请号：US14335401

申请日：2014-07-18

Applicant: Renesas Electronics Corporation

Inventor： Itaru YANAGI ,  Toshiyuki MINE ,  Hirotaka HAMAMURA ,  Digh HISAMOTO ,  Yasuhiro SHIMAMOTO

IPC: H01L29/792

CPC classification number: H01L29/792 ,  G11C16/0466 ,  H01L27/105 ,  H01L27/115 ,  H01L27/11521 ,  H01L27/11526 ,  H01L27/11568 ,  H01L27/11573 ,  H01L29/40114 ,  H01L29/40117 ,  H01L29/42344 ,  H01L29/513

Abstract: In a non-volatile memory in which writing/erasing is performed by changing a total charge amount by injecting electrons and holes into a silicon nitride film serving as a charge accumulation layer, in order to realize a high efficiency of a hole injection from a gate electrode, the gate electrode of a memory cell comprises a laminated structure made of a plurality of polysilicon films with different impurity concentrations, for example, a two-layered structure comprising a p-type polysilicon film with a low impurity concentration and a p|-type polysilicon film with a high impurity concentration deposited thereon.

Abstract translation: 在通过将电子和空穴注入到用作电荷累积层的氮化硅膜中来改变总电荷量进行写/擦除的非易失性存储器中，为了实现从栅极的空穴注入的高效率 电极，存储单元的栅电极包括由具有不同杂质浓度的多个多晶硅膜制成的层压结构，例如包括具有低杂质浓度的p型多晶硅膜和具有较低杂质浓度的双层结构的双层结构 沉积有高杂质浓度的多晶硅膜。

公开(公告)号：US20130341727A1

公开(公告)日：2013-12-26

申请号：US13945282

申请日：2013-07-18

Applicant: Renesas Electronics Corporation

Inventor： Yasuhiro SHIMAMOTO ,  Jiro YUGAMI ,  Masao INOUE ,  Masaharu MIZUTANI

IPC: H01L27/092

CPC classification number: H01L27/092 ,  H01L21/28035 ,  H01L21/28202 ,  H01L21/28229 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823842 ,  H01L21/823857 ,  H01L29/518 ,  H01L29/6659 ,  H01L29/7833

Abstract: Disclosed is a semiconductor device including a first MISFET of an n channel type and a second MISFET of a p channel type, each of the MISFETs being configured with a gate insulating film featuring a silicon oxide film or a silicon oxynitride film and a gate electrode including a conductive silicon film positioned on the gate insulating film. Metal elements such as Hf are introduced near the interface between the gate electrode and the gate insulating film in both the first and second MISFETs such that metal atoms with a surface density of 1×1013 to 5×1014 atoms/cm2 are contained near the interface and each of the first and second MISFETs having a channel region containing an impurity the concentration of which is equal to or lower than 1.2×1018/cm3.

Abstract translation: 公开了一种包括n沟道型的第一MISFET和ap沟道型的第二MISFET的半导体器件，每个MISFET被配置有具有硅氧化膜或氮氧化硅膜的栅极绝缘膜和包括 位于栅极绝缘膜上的导电硅膜。 金属元素如Hf在第一和第二MISFET中的栅电极和栅极绝缘膜之间的界面附近引入，使得表面密度为1×1013至5×1014原子/ cm2的金属原子包含在界面附近 并且第一和第二MISFET中的每一个具有含有浓度等于或低于1.2×1018 / cm3的杂质的沟道区。

公开(公告)号：US20130234236A1

公开(公告)日：2013-09-12

申请号：US13845005

申请日：2013-03-17

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Itaru YANAGI ,  Toshiyuki MINE ,  Hirotaka HAMAMURA ,  Digh HISAMOTO ,  Yasuhiro SHIMAMOTO

IPC: H01L29/792

CPC classification number: H01L29/792 ,  G11C16/0466 ,  H01L21/28273 ,  H01L21/28282 ,  H01L27/105 ,  H01L27/115 ,  H01L27/11521 ,  H01L27/11526 ,  H01L27/11568 ,  H01L27/11573 ,  H01L29/42344 ,  H01L29/513

Abstract: In a non-volatile memory in which writing/erasing is performed by changing a total charge amount by injecting electrons and holes into a silicon nitride film serving as a charge accumulation layer, in order to realize a high efficiency of a hole injection from a gate electrode, the gate electrode of a memory cell comprises a laminated structure made of a plurality of polysilicon films with different impurity concentrations, for example, a two-layered structure comprising a p-type polysilicon film with a low impurity concentration and a p+-type polysilicon film with a high impurity concentration deposited thereon.

Abstract translation: 在通过将电子和空穴注入到用作电荷累积层的氮化硅膜中来改变总电荷量进行写/擦除的非易失性存储器中，为了实现从栅极的空穴注入的高效率 电极，存储单元的栅电极包括由具有不同杂质浓度的多个多晶硅膜制成的层压结构，例如包括具有低杂质浓度的p型多晶硅膜和p +型的两层结构 沉积有高杂质浓度的多晶硅膜。