Abstract:
A programmable gain amplifier (PGA) circuit includes a gain adjust circuit and a gain select circuit that are both coupled to an output of an amplifier. The gain select circuit completes feedback to the amplifier while the gain adjust circuit is arranged to boost or cut the gain of the gain selection circuit. The gain adjust circuit can be arranged as a trim adjustment to the overall gain of the PGA circuit, where a different trim adjustment can be mapped to each gain setting such as from a look-up table. In other example implementations, the PGA circuit can periodically switch between multiple gain settings using a modulation scheme such that the overall gain is blended between the various gain settings according to a duty cycle, pulse-width, or delta-sigma modulation, with a time averaging effect on the overall gain of the PGA circuit.
Abstract:
Control circuitry handles inrush current, and may provide under voltage and/or over voltage monitoring and handling, as well as remote enable handling. The circuitry may advantageously employ a sense capacitor in parallel with an input capacitor (e.g., bulk input filter capacitor), and a current mirror to produce a signal proportional to input current. A clamp circuit may control a series pass device to regulate current in response to the proportional signal, or to interrupt current flow in response to an under voltage or over voltage condition or receipt of a signal indicative of a disable state. An enable signal may be summed into a comparator that handles under voltage condition determination.
Abstract:
An output stage of an amplifier circuit includes one or more output transistors that are selectively driven by a boosted drive circuit, where the boosted drive circuit is arranged such that the output range of the amplifier circuit is increased while maintaining reduced quiescent current. The drive signal to each output transistor is selectively increased only when demanded by the output load conditions. The threshold for boosting the drive signal can be adjusted for optimized performance. In one example, a class AB output stage includes a separate drive boost circuit for each output transistor. For this example, each drive boost circuit has a separate threshold for boosting each of the drive signals to the output transistors. The boosting can also be adjusted to optimize the differential input stage and current mirror maximum current requirement while maintaining minimum required bias currents.
Abstract:
Control circuitry handles inrush current, and may provide under voltage and/or over voltage monitoring and handling, as well as remote enable handling. The circuitry may advantageously employ a sense capacitor in parallel with an input capacitor (e.g., bulk input filter capacitor), and a current mirror to produce a signal proportional to input current. A clamp circuit may control a series pass device to regulate current in response to the proportional signal, or to interrupt current flow in response to an under voltage or over voltage condition or receipt of a signal indicative of a disable state. An enable signal may be summed into a comparator that handles under voltage condition determination.
Abstract:
An auxiliary power supply or bias voltage supply employs a step up switch mode DC/DC power converter topology to supply regulated bias supply voltages, from very low input voltages (e.g., less than 2V). The supply will synchronize to dynamic loads making it particularly useful in circuits with periodic high peak current power demands, for example, gate drive circuits employed in regulated switched mode power converters. When unladed, the supply will efficiently adjust its cycle period to the minimum required to maintain the desired boosted output voltage. Additional transformer windings or a charge pump may be used to generate additional vias voltage sources.
Abstract:
A programmable gain amplifier includes a first gain setting circuit and a second gain setting circuit that are both coupled to an output of an amplifier. A trim adjustment circuit is and arranged to complete feedback to the amplifier by digitally panning between the first gain setting and the second gain setting based on a trim setting. The trim setting can be provided by a look-up table that is indexed with gain settings. The first and the second gain setting circuits can each include an array of series coupled resistors, where a tap point from each array is selectively coupled to the trim adjustment circuit for adjusting the overall gain. The first and second gain setting circuits can be matched to one another, with the addition of a gain offset circuit that is configured to skew the nominal gain values between the first and second gain setting circuits.
Abstract:
An auxiliary power supply or bias voltage supply employs a step up switch mode DC/DC power converter topology to supply regulated bias supply voltages, from very low input voltages (e.g., less than 2V). The supply will synchronize to dynamic loads making it particularly useful in circuits with periodic high peak current power demands, for example, gate drive circuits employed in regulated switched mode power converters. When unladed, the supply will efficiently adjust its cycle period to the minimum required to maintain the desired boosted output voltage. Additional transformer windings or a charge pump may be used to generate additional vias voltage sources.
Abstract:
A programmable gain amplifier (PGA) circuit includes a gain adjust circuit and a gain select circuit that are both coupled to an output of an amplifier. The gain select circuit completes feedback to the amplifier while the gain adjust circuit is arranged to boost or cut the gain of the gain selection circuit. The gain adjust circuit can be arranged as a trim adjustment to the overall gain of the PGA circuit, where a different trim adjustment can be mapped to each gain setting such as from a look-up table. In other example implementations, the PGA circuit can periodically switch between multiple gain settings using a modulation scheme such that the overall gain is blended between the various gain settings according to a duty cycle, pulse-width, or delta-sigma modulation, with a time averaging effect on the overall gain of the PGA circuit.
Abstract:
A programmable gain amplifier (PGA) circuit includes a gain adjust circuit and a gain select circuit that are both coupled to an output of an amplifier. The gain select circuit completes feedback to the amplifier while the gain adjust circuit is arranged to boost or cut the gain of the gain selection circuit. The gain adjust circuit can be arranged as a trim adjustment to the overall gain of the PGA circuit, where a different trim adjustment can be mapped to each gain setting such as from a look-up table. In other example implementations, the PGA circuit can periodically switch between multiple gain settings using a modulation scheme such that the overall gain is blended between the various gain settings according to a duty cycle, pulse-width, or delta-sigma modulation, with a time averaging effect on the overall gain of the PGA circuit.
Abstract:
A programmable gain amplifier (PGA) circuit includes a gain adjust circuit and a gain select circuit that are both coupled to an output of an amplifier. The gain select circuit completes feedback to the amplifier while the gain adjust circuit is arranged to boost or cut the gain of the gain selection circuit. The gain adjust circuit can be arranged as a trim adjustment to the overall gain of the PGA circuit, where a different trim adjustment can be mapped to each gain setting such as from a look-up table. In other example implementations, the PGA circuit can periodically switch between multiple gain settings using a modulation scheme such that the overall gain is blended between the various gain settings according to a duty cycle, pulse-width, or delta-sigma modulation, with a time averaging effect on the overall gain of the PGA circuit.