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公开(公告)号:US20240407152A1
公开(公告)日:2024-12-05
申请号:US18642174
申请日:2024-04-22
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor: Eulji JEONG , Sukhoon KIM , Hyojung NOH , Sungnam LYU , Byounghoon LEE
IPC: H10B12/00
Abstract: A gate structure comprising: a first conductive pattern; a first seed pattern on a lower surface and a first portion of a sidewall of the first conductive pattern, wherein the first seed pattern includes a first material, and the first conductive pattern includes a second material that is different from the first material; and a gate insulation pattern that is in contact with a second portion of the sidewall of the first conductive pattern and the first seed pattern, wherein the first material has a first work function, and the second material has a second work function, and wherein the first work function is lower than the second work function.
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公开(公告)号:US20220415643A1
公开(公告)日:2022-12-29
申请号:US17660449
申请日:2022-04-25
Applicant: Semes Co., Ltd. , Samsung Electronics Co., Ltd.
Inventor: Hae-Won CHOI , Anton KORIAKIN , Sangjine Park PARK , Keonyoung KIM , Sukhoon KIM , Seohyun KIM , Young-Hoo KIM , Kuntack LEE , Jihoon JEONG
Abstract: In a substrate processing method, a rinse process using a rinse solution is performed on a development-processed photoresist pattern on a substrate. A substitution process including a first substitution step using a mixed solution of a non-polar organic solvent and a surfactant and a second substitution step using the non-polar organic solvent is performed on the substrate. The substitution process is performed a plurality of times until the rinse solution remaining on the substrate is less than a predetermined value. A supercritical fluid drying process is performed on the substrate to dry the non-polar organic solvent remaining on the substrate.
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公开(公告)号:US20210102285A1
公开(公告)日:2021-04-08
申请号:US16898609
申请日:2020-06-11
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor: Jeong-Heon PARK , Whankyun KIM , Sukhoon KIM , Junho JEONG
IPC: C23C14/46 , H01L21/687
Abstract: An ion beam deposition apparatus includes a substrate assembly to secure a substrate, a target assembly slanted with respect to the substrate assembly, the target assembly including a target with deposition materials, an ion gun to inject ion beams onto the target, such that ions of the deposition materials are discharged toward the substrate assembly to form a thin layer on the substrate, and a substrate heater to heat the substrate to a deposition temperature higher than a room temperature.
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公开(公告)号:US20220344347A1
公开(公告)日:2022-10-27
申请号:US17520868
申请日:2021-11-08
Applicant: Samsung Electronics Co., Ltd.
Inventor: Jaewha PARK , Moonkeun KIM , Sukhoon KIM , Dongchan LIM
IPC: H01L27/108
Abstract: A semiconductor device manufacturing method according to the exemplary embodiments of the disclosure includes patterning a substrate, thereby forming an active pattern, forming a trench penetrating the active pattern, forming a support layer covering the trench, forming a first opening at the support layer, forming a gate electrode layer filling the trench through the first opening, and forming a bit line structure electrically connected to the active pattern. The support layer includes a base portion covering a top surface of the active pattern, and a support disposed in the trench.
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公开(公告)号:US20220208558A1
公开(公告)日:2022-06-30
申请号:US17559766
申请日:2021-12-22
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor: Sangjine PARK , Seohyun KIM , Sukhoon KIM , Jihoon JEONG , Younghoo KIM , Kuntack LEE
IPC: H01L21/3213 , H01L21/311 , H01L21/308 , G03F7/32 , G03F7/20
Abstract: A substrate processing method includes providing a surface tension reducing agent as a gas onto a substrate, the substrate having an exposed photoresist layer and layer of developer on the exposed photoresist layer, and causing a bulk flow of the developer in order to remove the developer from the substrate.
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公开(公告)号:US20240339334A1
公开(公告)日:2024-10-10
申请号:US18747951
申请日:2024-06-19
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor: Sangjine PARK , Seohyun KIM , Sukhoon KIM , Jihoon JEONG , Younghoo KIM , Kuntack LEE
IPC: H01L21/3213 , G03F7/20 , G03F7/30 , G03F7/32 , H01L21/308 , H01L21/311
CPC classification number: H01L21/32139 , G03F7/2004 , G03F7/3021 , G03F7/325 , H01L21/308 , H01L21/31144
Abstract: A substrate processing apparatus includes a processing chamber having an internal space and a substrate support within the internal space, a surface tension reducing agent supply system that supplies a surface tension reducing agent as a gas to the processing chamber, and a controller that controls the supply of the surface tension reducing agent via the surface tension reducing agent supply system. The surface tension reducing agent supply system includes at least one supply port that is configured to supply the surface tension reducing agent to the internal space and at least one discharge port that is configured to remove developer from the internal space.
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公开(公告)号:US20230411161A1
公开(公告)日:2023-12-21
申请号:US18196098
申请日:2023-05-11
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor: Minsik KIM , Gwanhyoung LEE , Sukhoon KIM , Yongjun SHIN
IPC: H01L21/3065 , H01L29/20 , H01L29/423 , H01L21/768 , H01L21/311 , H01L21/02
CPC classification number: H01L21/3065 , H01L29/2003 , H01L29/42364 , H01L21/02107 , H01L21/76897 , H01L21/31116 , H01L21/76829
Abstract: In a method, an electrode layer and an insulation layer are alternately and repeatedly stacked on a substrate. A first insulation layer is etched through a first dry etching process using an etching gas including fluorine to form an opening exposing a first electrode layer. The first electrode layer exposed by the opening is partially removed through an RIE process using oxygen and/or hydrogen plasma to enlarge the opening so that a second insulation layer is exposed. The second insulation layer exposed by the opening is etched through a second dry etching process using an etching gas including fluorine to enlarge the opening so that a second electrode layer is exposed. A contact plug is formed in the enlarged opening.
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公开(公告)号:US20230397393A1
公开(公告)日:2023-12-07
申请号:US18207689
申请日:2023-06-09
Applicant: Samsung Electronics Co., Ltd.
Inventor: Jaewha PARK , Moonkeun KIM , Sukhoon KIM , Dongchan LIM
IPC: H10B12/00
CPC classification number: H10B12/053 , H10B12/34 , H10B12/315 , H10B12/482
Abstract: A semiconductor device manufacturing method according to the exemplary embodiments of the disclosure includes patterning a substrate, thereby forming an active pattern, forming a trench penetrating the active pattern, forming a support layer covering the trench, forming a first opening at the support layer, forming a gate electrode layer filling the trench through the first opening, and forming a bit line structure electrically connected to the active pattern. The support layer includes a base portion covering a top surface of the active pattern, and a support disposed in the trench.
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