公开(公告)号：US10008273B2

公开(公告)日：2018-06-26

申请号：US15181346

申请日：2016-06-13

Applicant: SanDisk Technologies LLC

Inventor： Biswajit Ray ,  Gerrit Jan Hemink ,  Mohan Dunga ,  Bijesh Rajamohanan ,  Changyuan Chen

IPC: G11C16/28 ,  G06F11/10 ,  G11C29/52 ,  G11C16/04 ,  G11C16/24 ,  G11C16/26 ,  G11C29/02 ,  G11C7/12 ,  G11C29/12

CPC classification number: G11C16/28 ,  G06F11/1068 ,  G11C7/12 ,  G11C16/0483 ,  G11C16/24 ,  G11C16/26 ,  G11C29/028 ,  G11C29/52 ,  G11C2029/1204

Abstract: Apparatuses, systems, methods, and computer program products are disclosed for read level determination. A block of non-volatile storage cells has a plurality of bit lines. A controller for a block is configured to perform a first read on a set of storage cells using a first read level for the bit lines. A controller is configured to determine a second read level for at least a portion of the bit lines based at least partially on a first read. A controller is configured to perform a second read on a set of storage cells using a second read level for at least a portion of bit lines.

公开(公告)号：US20190006005A1

公开(公告)日：2019-01-03

申请号：US15635935

申请日：2017-06-28

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Bijesh Rajamohanan ,  Juan Pablo Saenz

IPC: G11C13/00

CPC classification number: G11C13/0064 ,  G11C13/0007 ,  G11C13/0028 ,  G11C13/004 ,  G11C13/0069 ,  G11C2013/0083 ,  G11C2213/71

Abstract: After programming a set of resistive memory cells in a resistive memory device, the programmed states and the functionality of each resistive memory cell in the programmed set can be verified by a primary determination method and a secondary determination method. The primary determination method employs the step of determining whether a measured electrical current at a preset read voltage for the selected resistive memory cell is within electrical current specification for the selected resistive state. If the selected cell fails the primary determination method, the second determination method is performed, which includes determining whether a measured threshold voltage for the selected resistive memory cell is within threshold voltage specification for the selected resistive state. If the selected cell fails both methods, the selected cell is identified as a non-functional resistive memory cell. Otherwise, the selected cell is identified as an operational cell.

公开(公告)号：US10256402B1

公开(公告)日：2019-04-09

申请号：US15714246

申请日：2017-09-25

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Bijesh Rajamohanan ,  Juan Saenz

IPC: H01L45/00 ,  H01L27/112 ,  H01L29/10 ,  C01B13/34 ,  C01F17/00

Abstract: A method of operating a resistive memory device includes providing a resistive memory device including an array of resistive memory cells, where each of the resistive memory cells includes a resistive memory material having at least two different resistive states, performing a first mode read operation on a group of resistive memory cells within the array, determining a bit error rate for data generated by the first mode read operation, determining whether the determined bit error rate is below a predetermined limit, and performing a second mode read operation on the group of resistive memory cells within the array based on a threshold voltage if the determined bit error rate is above the predetermined limit.

公开(公告)号：US20190130971A1

公开(公告)日：2019-05-02

申请号：US15800037

申请日：2017-10-31

Applicant: SanDisk Technologies LLC

Inventor： Bijesh Rajamohanan

IPC: G11C13/00

Abstract: Apparatuses, systems, and methods are disclosed for write-time prevention of data retention failures for non-volatile memory. An apparatus may include an array of non-volatile memory cells and a controller. A controller may be configured to perform a write operation for at least one cell. A controller may be configured to identify, during a write operation, one or more cells for which a characteristic of the one or more identified cells is associated with data retention failure. A controller may be configured to modify a write operation for one or more identified cells.

公开(公告)号：US10354728B2

公开(公告)日：2019-07-16

申请号：US15635935

申请日：2017-06-28

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Bijesh Rajamohanan ,  Juan Pablo Saenz

IPC: G11C13/00

Abstract: After programming a set of resistive memory cells in a resistive memory device, the programmed states and the functionality of each resistive memory cell in the programmed set can be verified by a primary determination method and a secondary determination method. The primary determination method employs the step of determining whether a measured electrical current at a preset read voltage for the selected resistive memory cell is within electrical current specification for the selected resistive state. If the selected cell fails the primary determination method, the second determination method is performed, which includes determining whether a measured threshold voltage for the selected resistive memory cell is within threshold voltage specification for the selected resistive state. If the selected cell fails both methods, the selected cell is identified as a non-functional resistive memory cell. Otherwise, the selected cell is identified as an operational cell.

公开(公告)号：US20190066781A1

公开(公告)日：2019-02-28

申请号：US15691801

申请日：2017-08-31

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Bijesh Rajamohanan ,  Srinitya Musunuru ,  Emmanuelle Merced-Grafals

IPC: G11C13/00

Abstract: A memory device is provided that includes a memory array having a plurality of reversible resistance-switching memory cells, and a memory controller coupled to the memory array. The memory controller is adapted to program a first reversible resistance-switching memory cell in the memory array to a predetermined data state, determine a program loop count associated with the program step, and retire the first reversible resistance-switching memory cell from further use for host data storage based on the associated program loop count.

公开(公告)号：US20180138292A1

公开(公告)日：2018-05-17

申请号：US15349382

申请日：2016-11-11

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Alvaro Padilla ,  Bijesh Rajamohanan

IPC: H01L29/66 ,  H01L27/24 ,  H01L27/115 ,  H01L45/00

CPC classification number: H01L45/16 ,  H01L27/2454 ,  H01L27/249 ,  H01L45/04 ,  H01L45/06 ,  H01L45/10 ,  H01L45/1226 ,  H01L45/145 ,  H01L45/146 ,  H01L45/147

Abstract: A method is provided that includes forming a bit line above a substrate, forming a word line above the substrate, and forming a non-volatile memory cell between the bit line and the word line. The non-volatile memory cell includes a non-volatile memory material coupled in series with an isolation element. The isolation element includes a first portion disposed between a first electrode and a second electrode, the first electrode includes a first material having a first work function, the second electrode includes a second material having second work function, and the first work function does not equal the second work function.

公开(公告)号：US20170358365A1

公开(公告)日：2017-12-14

申请号：US15181346

申请日：2016-06-13

Applicant: SanDisk Technologies LLC

Inventor： Biswajit Ray ,  Gerrit Jan Hemink ,  Mohan Dunga ,  Bijesh Rajamohanan ,  Changyuan Chen

IPC: G11C16/28 ,  G06F11/10 ,  G11C29/52

CPC classification number: G11C16/28 ,  G06F11/1068 ,  G11C7/12 ,  G11C16/0483 ,  G11C16/24 ,  G11C16/26 ,  G11C29/028 ,  G11C29/52 ,  G11C2029/1204

Abstract: Apparatuses, systems, methods, and computer program products are disclosed for read level determination. A block of non-volatile storage cells has a plurality of bit lines. A controller for a block is configured to perform a first read on a set of storage cells using a first read level for the bit lines. A controller is configured to determine a second read level for at least a portion of the bit lines based at least partially on a first read. A controller is configured to perform a second read on a set of storage cells using a second read level for at least a portion of bit lines.