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公开(公告)号：US10032908B1
公开(公告)日：2018-07-24
申请号：US15400244
申请日：2017-01-06
发明人： Perumal Ratnam , Christopher Petti , Juan Saenz , Guangle Zhou , Abhijit Bandyopadhyay , Tanmay Kumar
IPC分类号： H01L29/78 , H01L27/24 , H01L29/423 , H01L23/528 , H01L29/66
摘要： A matrix rail structure is formed over a substrate. The matrix rail structure includes a pair of lengthwise sidewalls that extend along a first horizontal direction and comprises, or is at least partially subsequently replaced with, a set of at least one gate electrode rail extending along the first horizontal direction and straight-sidewalled gate dielectrics. A pair of vertical semiconductor channel strips and a pair of laterally-undulating gate dielectrics can be formed on sidewalls of the matrix rail structure for each vertical field effect transistor. At least one laterally-undulating gate electrode extending along the first horizontal direction is formed on the laterally-undulating gate dielectrics. Bottom active regions and top active regions are formed at end portions of the vertical semiconductor channel strips. The vertical field effect transistors can be formed as a two-dimensional array, and may be employed as access transistors for a three-dimensional memory device.
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公开(公告)号：US20180166559A1
公开(公告)日：2018-06-14
申请号：US15376916
申请日：2016-12-13
发明人： Guangle Zhou , Chuanbin Pan , Juan Saenz , Tanmay Kumar
IPC分类号： H01L29/66 , H01L27/11521 , H01L27/11568 , H01L27/11556 , H01L27/11582 , H01L27/24 , H01L45/00
CPC分类号： H01L29/66666 , H01L27/11556 , H01L27/11582 , H01L27/2454 , H01L27/249 , H01L29/7827 , H01L45/04 , H01L45/12 , H01L45/1226 , H01L45/146 , H01L45/147
摘要： A method is provided that includes forming a word line above a substrate, the word line disposed in a first direction, the word line including a first portion including a first conductive material and a second portion including a second conductive material, forming a bit line above the substrate, the bit line disposed in a second direction perpendicular to the first direction, forming a nonvolatile memory material between the word line and the bit line, the nonvolatile memory material including a semiconductor material layer and a conductive oxide material layer, the semiconductor material layer disposed adjacent the second portion of the word line, and forming a memory cell including the nonvolatile memory material at an intersection of the local bit line and the word line.
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公开(公告)号：US10283567B2
公开(公告)日：2019-05-07
申请号：US15441284
申请日：2017-02-24
发明人： Juan Saenz , Deepak Kamalanathan , Guangle Zhou , Ming-Che Wu , Tanmay Kumar
摘要： A method is provided that includes forming a word line above a substrate, the word line disposed in a first direction, forming a bit line above the substrate, the bit line disposed in a second direction perpendicular to the first direction, forming a nonvolatile memory material between the word line and the bit line, the nonvolatile memory material including a semiconductor material layer and conductive oxide material layer, forming a first barrier material layer between the word line and the nonvolatile memory material, forming a second barrier material layer between the bit line and the nonvolatile memory material, and forming a memory cell including the nonvolatile memory material at an intersection of the bit line and the word line.
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公开(公告)号：US20180358550A1
公开(公告)日：2018-12-13
申请号：US15621305
申请日：2017-06-13
发明人： Deepak Kamalanathan , Juan Saenz
CPC分类号： H01L45/08 , H01L27/2481 , H01L45/146 , H01L45/1683
摘要： Systems and methods for providing a Barrier Modulated Cell (BMC) structure with reduced shifting in stored memory cell resistance levels over time are described. The BMC structure may comprise a reversible resistance-switching memory element within a memory array comprising a first conductive metal oxide (e.g., titanium oxide) in series with an alternating stack of one or more layers of an amorphous low bandgap material (e.g., germanium) with one or more layers of a second conductive metal oxide (e.g., aluminum oxide). The BMC structure may include a barrier layer comprising a first conductive metal oxide, such as titanium oxide or strontium titanate, in series with a germanium stack that includes a layer of amorphous germanium or amorphous silicon germanium paired with a second conductive metal oxide. The second conductive metal oxide (e.g., aluminum oxide) may be different from the first conductive metal oxide (e.g., titanium oxide).
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公开(公告)号：US20180315794A1
公开(公告)日：2018-11-01
申请号：US15498255
申请日：2017-04-26
摘要： A method is provided that includes forming a word line above a substrate, the word line disposed in a first direction, forming a bit line above the substrate, the bit line disposed in a second direction perpendicular to the first direction, forming a nonvolatile memory material between the word line and the bit line, and forming a memory cell including the nonvolatile memory material at an intersection of the bit line and the word line. The nonvolatile memory material includes a semiconductor material layer, and a conductive oxide material layer including a first conductive oxide material layer portion and a second conductive oxide material layer portion. The method also includes forming a barrier material layer between the first conductive oxide material layer portion and the second conductive oxide material layer portion.
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公开(公告)号：US10283708B2
公开(公告)日：2019-05-07
申请号：US15452373
申请日：2017-03-07
发明人： Ming-Che Wu , Deepak Kamalanathan , Juan Saenz , Tanmay Kumar
IPC分类号： H01L45/00 , H01L27/24 , H01L27/105 , G11C13/00 , H01L27/115
摘要： A method is provided that includes forming a word line above a substrate, the word line disposed in a first direction, forming a bit line above the substrate, the bit line disposed in a second direction perpendicular to the first direction, forming a nonvolatile memory material between the word line and the bit line, and forming a memory cell including the nonvolatile memory material at an intersection of the bit line and the word line. The word line includes a first portion and a second portion including an electrically conductive carbon-containing material. The nonvolatile memory material includes a semiconductor material layer and a conductive oxide material layer, with the semiconductor material layer disposed adjacent the second portion of the word line.
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公开(公告)号：US10153430B1
公开(公告)日：2018-12-11
申请号：US15621305
申请日：2017-06-13
发明人： Deepak Kamalanathan , Juan Saenz
CPC分类号： H01L45/08 , H01L27/2481 , H01L45/146 , H01L45/1683
摘要： Systems and methods for providing a Barrier Modulated Cell (BMC) structure with reduced shifting in stored memory cell resistance levels over time are described. The BMC structure may comprise a reversible resistance-switching memory element within a memory array comprising a first conductive metal oxide (e.g., titanium oxide) in series with an alternating stack of one or more layers of an amorphous low bandgap material (e.g., germanium) with one or more layers of a second conductive metal oxide (e.g., aluminum oxide). The BMC structure may include a barrier layer comprising a first conductive metal oxide, such as titanium oxide or strontium titanate, in series with a germanium stack that includes a layer of amorphous germanium or amorphous silicon germanium paired with a second conductive metal oxide. The second conductive metal oxide (e.g., aluminum oxide) may be different from the first conductive metal oxide (e.g., titanium oxide).
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公开(公告)号：US20180261766A1
公开(公告)日：2018-09-13
申请号：US15452373
申请日：2017-03-07
发明人： Ming-Che Wu , Deepak Kamalanathan , Juan Saenz , Tanmay Kumar
CPC分类号： H01L45/1608 , G11C7/18 , G11C8/14 , G11C13/0007 , G11C2213/35 , G11C2213/71 , H01L27/2436 , H01L27/2454 , H01L27/249 , H01L45/04 , H01L45/06 , H01L45/1206 , H01L45/1233 , H01L45/124 , H01L45/146 , H01L45/16
摘要： A method is provided that includes forming a word line above a substrate, the word line disposed in a first direction, forming a bit line above the substrate, the bit line disposed in a second direction perpendicular to the first direction, forming a nonvolatile memory material between the word line and the bit line, and forming a memory cell including the nonvolatile memory material at an intersection of the bit line and the word line. The word line includes a first portion and a second portion including an electrically conductive carbon-containing material. The nonvolatile memory material includes a semiconductor material layer and a conductive oxide material layer, with the semiconductor material layer disposed adjacent the second portion of the word line.
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公开(公告)号：US10319437B2
公开(公告)日：2019-06-11
申请号：US15710247
申请日：2017-09-20
发明人： Juan Saenz , Christopher J Petti
IPC分类号： G11C13/00
摘要： Technology is described for identifying non-volatile memory cells having data that should be refreshed. The technology could be used to identify which groups of memory cells that store cold data should have a data refresh. In one aspect, a non-volatile storage device has at least one monitor memory cell associated with a group of data memory cells. The non-volatile storage device may use different programming techniques to program the data and monitor memory cells. In one aspect, the programming technique used for the monitor memory cell is less stable with respect to state than the technique used to program the associated data memory cells. The state of the monitor memory cell may change in a predictable manner, such that the state of the monitor cell may be sensed periodically to determine whether the associated data memory cells should be refreshed.
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公开(公告)号：US10256402B1
公开(公告)日：2019-04-09
申请号：US15714246
申请日：2017-09-25
发明人： Bijesh Rajamohanan , Juan Saenz
IPC分类号： H01L45/00 , H01L27/112 , H01L29/10 , C01B13/34 , C01F17/00
摘要： A method of operating a resistive memory device includes providing a resistive memory device including an array of resistive memory cells, where each of the resistive memory cells includes a resistive memory material having at least two different resistive states, performing a first mode read operation on a group of resistive memory cells within the array, determining a bit error rate for data generated by the first mode read operation, determining whether the determined bit error rate is below a predetermined limit, and performing a second mode read operation on the group of resistive memory cells within the array based on a threshold voltage if the determined bit error rate is above the predetermined limit.
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