公开(公告)号：US20200258876A1

公开(公告)日：2020-08-13

申请号：US16847857

申请日：2020-04-14

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Naohiro HOSODA ,  Kazuma SHIMAMOTO ,  Tetsuya SHIRASU ,  Yuji FUKANO ,  Akio NISHIDA

IPC: H01L25/18 ,  G11C16/24 ,  H01L27/11556 ,  H01L27/11519 ,  H01L27/11573 ,  H01L27/11524 ,  H01L27/1157 ,  H01L27/11565 ,  G11C16/08 ,  H01L27/11529 ,  H01L27/11582 ,  G11C16/26

Abstract: A bonded assembly includes a memory die including a three-dimensional memory array located on a first single crystalline semiconductor substrate, and a logic die including a peripheral circuitry located on a second single crystalline semiconductor substrate and bonded to the memory die. The three-dimensional memory array includes word lines and bit lines. The logic die includes field effect transistors having semiconductor channels configured to flow electrical current along a channel direction that is parallel to the bit lines or word lines. Different crystallographic orientations are used for the first and second single crystalline semiconductor substrates. The crystallographic orientations of the first single crystalline semiconductor substrate are selected to minimize stress deformation of the memory chip, while the crystallographic orientations of the second single crystalline semiconductor substrate are selected to maximize device performance of the peripheral circuitry.

公开(公告)号：US20200227397A1

公开(公告)日：2020-07-16

申请号：US16249423

申请日：2019-01-16

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Shinsuke YADA ,  Masanori TSUTSUMI ,  Sayako NAGAMINE ,  Yuji FUKANO ,  Akio NISHIDA ,  Christopher J. PETTI

IPC: H01L25/18 ,  H01L27/11556 ,  H01L23/00 ,  H01L23/528 ,  H01L23/522 ,  H01L29/10 ,  H01L25/065 ,  H01L25/00 ,  H01L21/683 ,  H01L27/11519 ,  H01L27/11565 ,  H01L27/11521 ,  H01L27/11526 ,  H01L27/11568 ,  H01L27/11573 ,  H01L27/11582

Abstract: Memory dies configured for multi-stacking within a bonded assembly may be provided without using through-substrate vias that extend through semiconductor substrates. A first memory die may be provided by forming interconnect-side bonding pads on a three-dimensional memory device that overlies a semiconductor substrate. A support die including a peripheral circuitry is boned to the interconnect-side bonding pads. The semiconductor substrate is removed, and array-side bonding pads are formed on an opposite side of the interconnect-side bonding pads. Electrically conductive paths that do not pass through any semiconductor material portion are formed between the interconnect-side bonding pads and the array-side bonding pads, thereby avoiding costly formation of through-substrate via structures that extend through any semiconductor substrate. A second memory die may be bonded to the first memory die to provide stacking of multiple memory dies. Semiconductor substrates may be removed from each memory die upon bonding to a pre-existing assembly.

公开(公告)号：US20200251485A1

公开(公告)日：2020-08-06

申请号：US16268132

申请日：2019-02-05

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Manabu KAKAZU ,  Takashi YUDA ,  Yuji FUKANO

IPC: H01L27/11582 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/1157 ,  H01L23/522 ,  H01L23/528 ,  H01L23/00 ,  H01L21/28 ,  H01L21/768

Abstract: A three-dimensional memory device includes a vertical semiconductor channel surrounding a vertical dielectric core. Laterally extending dielectric pegs structurally support the vertical semiconductor channel and the vertical dielectric core. The vertical semiconductor channel may be a single crystalline semiconductor channel.

公开(公告)号：US20200235123A1

公开(公告)日：2020-07-23

申请号：US16816552

申请日：2020-03-12

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Kenji SUGIURA ,  Mitsuteru MUSHIGA ,  Yuji FUKANO ,  Akio NISHIDA

IPC: H01L27/11582 ,  H01L21/768 ,  H01L27/11568 ,  H01L27/108 ,  H01L27/11556 ,  H01L27/105 ,  H01L23/522

Abstract: A vertically alternating stack of insulating layers and dielectric spacer material layers is formed over a semiconductor substrate. The vertically alternating stack is patterned into a first alternating stack located at a center region of a memory die and a second alternating stack that laterally encloses the first alternating stack. Memory stack structures are formed through the first alternating stack, and portions of the dielectric spacer material layers in the first alternating stack are replaced with electrically conductive layers while maintaining the second alternating stack intact. At least one metallic wall structure is formed through the second alternating stack. An edge seal assembly is provided, which includes at least one vertical stack of metallic seal structures. Each vertical stack of metallic seal structures vertically extends contiguously from a top surface of the semiconductor substrate to a bonding-side surface of the memory die, and includes a respective metallic wall structure.

公开(公告)号：US20190198515A1

公开(公告)日：2019-06-27

申请号：US15850073

申请日：2017-12-21

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Naohiro HOSODA ,  Keisuke SHIGEMURA ,  Junichi ARIYOSHI ,  Kazuki KAJITANI ,  Yuji FUKANO

IPC: H01L27/11556 ,  H01L27/11519 ,  H01L27/11565 ,  H01L27/11582 ,  H01L27/11524 ,  H01L27/1157 ,  H01L21/265 ,  H01L21/266

CPC classification number: H01L27/11556 ,  H01L21/26513 ,  H01L21/266 ,  H01L27/11519 ,  H01L27/11524 ,  H01L27/11565 ,  H01L27/1157 ,  H01L27/11582 ,  H01L29/408

Abstract: A memory device contains a stack of insulating layers and electrically conductive word line layers, at least one first drain select gate electrode located over the stack and extending through a first drain select transistor and a second drain select transistor, at least one second drain select gate electrode located between the first drain select electrode and the stack, and extending through a third drain select transistor and a fourth drain select transistor. The first drain select transistor and the third drain select transistor are located in a first NAND memory string. The second drain select transistor and the fourth drain select transistor are located in a second NAND memory string different from the first NAND memory string. The first drain select transistor has a higher threshold voltage than the second drain select transistor. The third drain select transistor has a lower threshold voltage than the fourth drain select transistor.