公开(公告)号：US20180006049A1

公开(公告)日：2018-01-04

申请号：US15704370

申请日：2017-09-14

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Takashi INOMATA ,  Nobuo HIRONAGA ,  Junichi ARIYOSHI ,  Tadashi NAKAMURA

IPC: H01L27/11556 ,  H01L27/1157 ,  H01L27/11582 ,  H01L23/528 ,  H01L23/522 ,  H01L21/768 ,  H01L27/11524 ,  H01L27/11519 ,  H01L27/11565

CPC classification number: H01L27/11556 ,  H01L21/76805 ,  H01L21/76816 ,  H01L21/76831 ,  H01L21/76877 ,  H01L23/5226 ,  H01L23/5283 ,  H01L27/11519 ,  H01L27/11524 ,  H01L27/11565 ,  H01L27/1157 ,  H01L27/11575 ,  H01L27/11582 ,  H01L29/7926

Abstract: A monolithic three-dimensional memory device includes a first alternating stack of first insulating layers and first electrically conductive layers located over a top surface of a substrate, an insulating cap layer overlying the first alternating stack, a second alternating stack of second insulating layers and second electrically conductive layers and overlying the insulating cap layer, memory openings extending through the second alternating stack, the insulating cap layer, and the first alternating stack, memory stack structures located within the memory openings, and annular spacers located within the insulating cap layer and laterally surrounding a respective one of the memory stack structures.

公开(公告)号：US20190267461A1

公开(公告)日：2019-08-29

申请号：US15906109

申请日：2018-02-27

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Shinsuke YADA ,  Xiaolong HU ,  Junichi ARIYOSHI

IPC: H01L29/423 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/11529 ,  H01L27/11519 ,  H01L27/1157 ,  H01L27/11582 ,  H01L27/11573 ,  H01L27/11565 ,  H01L21/28

Abstract: A three-dimensional memory device includes an alternating stack of insulating layers and electrically conductive layers located over a substrate. An insulating fill material layer and drain select gate electrodes are located over the alternating stack. A group of memory stack structures extends through the alternating stack, and is arranged as rows of memory stack structures. Each memory stack structure is entirely encircled laterally by a respective one of the drain select gate electrodes. The insulating fill material layer includes a drain select level isolation structure extending between neighboring rows of memory stack structures and including a pair of sidewalls containing a respective laterally alternating sequence of planar vertical sidewall portions and concave vertical sidewall portions, and a drain select level field portion adjoined to the drain select level isolation portion.

公开(公告)号：US20180138194A1

公开(公告)日：2018-05-17

申请号：US15496359

申请日：2017-04-25

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Keisuke SHIGEMURA ,  Junichi ARIYOSHI ,  Masanori TSUTSUMI ,  Michiaki SANO ,  Yanli ZHANG ,  Raghuveer S. MAKALA

IPC: H01L27/11582 ,  H01L27/11556 ,  H01L29/423 ,  H01L23/528 ,  H01L23/532 ,  H01L21/28 ,  H01L27/11524 ,  H01L21/768 ,  H01L21/311 ,  H01L27/1157 ,  H01L27/11526 ,  H01L27/11573 ,  H01L27/11519 ,  H01L27/11565

CPC classification number: H01L27/11582 ,  H01L21/28008 ,  H01L21/31111 ,  H01L21/76843 ,  H01L21/76877 ,  H01L23/528 ,  H01L23/53266 ,  H01L27/11519 ,  H01L27/11524 ,  H01L27/11526 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/1157 ,  H01L27/11573 ,  H01L29/42324 ,  H01L29/4234

Abstract: A three-dimensional memory device includes an alternating stack of insulating layers and electrically conductive layers located over a substrate, the alternating stack having a memory array region and a contact region containing stepped surfaces, and memory stack structures having a semiconductor channel and a memory film extending through the memory array region of the alternating stack. The electrically conductive layers include a drain select gate electrode and word lines, where the drain select gate electrode is thicker than each of the word lines.

公开(公告)号：US20190198515A1

公开(公告)日：2019-06-27

申请号：US15850073

申请日：2017-12-21

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Naohiro HOSODA ,  Keisuke SHIGEMURA ,  Junichi ARIYOSHI ,  Kazuki KAJITANI ,  Yuji FUKANO

IPC: H01L27/11556 ,  H01L27/11519 ,  H01L27/11565 ,  H01L27/11582 ,  H01L27/11524 ,  H01L27/1157 ,  H01L21/265 ,  H01L21/266

CPC classification number: H01L27/11556 ,  H01L21/26513 ,  H01L21/266 ,  H01L27/11519 ,  H01L27/11524 ,  H01L27/11565 ,  H01L27/1157 ,  H01L27/11582 ,  H01L29/408

Abstract: A memory device contains a stack of insulating layers and electrically conductive word line layers, at least one first drain select gate electrode located over the stack and extending through a first drain select transistor and a second drain select transistor, at least one second drain select gate electrode located between the first drain select electrode and the stack, and extending through a third drain select transistor and a fourth drain select transistor. The first drain select transistor and the third drain select transistor are located in a first NAND memory string. The second drain select transistor and the fourth drain select transistor are located in a second NAND memory string different from the first NAND memory string. The first drain select transistor has a higher threshold voltage than the second drain select transistor. The third drain select transistor has a lower threshold voltage than the fourth drain select transistor.