公开(公告)号：US20220059454A1

公开(公告)日：2022-02-24

申请号：US16999388

申请日：2020-08-21

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Haruki SUWA ,  Keisuke SHIGEMURA ,  Akihiro SHIMADA

IPC: H01L23/522 ,  H01L27/11582 ,  H01L27/11519 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/1157

Abstract: A three-dimensional memory device includes an alternating stack of insulating layers and electrically conductive layers containing steps, memory stack structures extending through the alternating stack, a first contact via structure which contacts a top surface of a respective upper electrically conductive layer in a first step, a first dielectric spacer which does not contact any of the electrically conductive layers other than the respective upper electrically conductive layer in the first step, a second contact via structure which contacts a top surface of a respective lower electrically conductive layer in the first step, and a second dielectric spacer which extends through the respective upper electrically conductive layer, and which contacts the respective lower electrically conductive layer.

公开(公告)号：US20180138194A1

公开(公告)日：2018-05-17

申请号：US15496359

申请日：2017-04-25

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Keisuke SHIGEMURA ,  Junichi ARIYOSHI ,  Masanori TSUTSUMI ,  Michiaki SANO ,  Yanli ZHANG ,  Raghuveer S. MAKALA

IPC: H01L27/11582 ,  H01L27/11556 ,  H01L29/423 ,  H01L23/528 ,  H01L23/532 ,  H01L21/28 ,  H01L27/11524 ,  H01L21/768 ,  H01L21/311 ,  H01L27/1157 ,  H01L27/11526 ,  H01L27/11573 ,  H01L27/11519 ,  H01L27/11565

CPC classification number: H01L27/11582 ,  H01L21/28008 ,  H01L21/31111 ,  H01L21/76843 ,  H01L21/76877 ,  H01L23/528 ,  H01L23/53266 ,  H01L27/11519 ,  H01L27/11524 ,  H01L27/11526 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/1157 ,  H01L27/11573 ,  H01L29/42324 ,  H01L29/4234

Abstract: A three-dimensional memory device includes an alternating stack of insulating layers and electrically conductive layers located over a substrate, the alternating stack having a memory array region and a contact region containing stepped surfaces, and memory stack structures having a semiconductor channel and a memory film extending through the memory array region of the alternating stack. The electrically conductive layers include a drain select gate electrode and word lines, where the drain select gate electrode is thicker than each of the word lines.

公开(公告)号：US20240107758A1

公开(公告)日：2024-03-28

申请号：US17936012

申请日：2022-09-28

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Hiroyuki OGAWA ,  Masato MIYAMOTO ,  Keisuke SHIGEMURA

IPC: H01L27/11582 ,  H01L23/522 ,  H01L23/528 ,  H01L27/11519 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/1157

CPC classification number: H01L27/11582 ,  H01L23/5226 ,  H01L23/5283 ,  H01L27/11519 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/1157

Abstract: A method of forming a three-dimensional semiconductor device includes forming an alternating stack of insulating layers and spacer material layers over a substrate, forming memory openings formed in the memory array region and monitor openings formed in a monitor region though the alternating stack, forming memory opening fill structures in the memory openings, forming monitor opening fill structures by depositing a monitor opening fill material in the monitor openings, recessing first portions of the alternating stack in a contact region and second portions of the alternating stack in the monitor region, and determining at least one characteristic of the recessed surfaces of the monitor opening fill structures. At least one characteristic of the memory openings or memory opening fill structures may be determined based on the determining at least one characteristic of the recessed surfaces of the monitor opening fill structures.

公开(公告)号：US20210358937A1

公开(公告)日：2021-11-18

申请号：US17134938

申请日：2020-12-28

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Kohei YAMAGUCHI ,  Keisuke SHIGEMURA ,  Kengo KAJIWARA

IPC: H01L27/11575 ,  H01L27/11556 ,  H01L27/11529 ,  H01L27/11582 ,  H01L23/00

Abstract: A row of backside support pillar structures is formed through a first-tier alternating stack of first-tier insulating layers and first-tier sacrificial material layers. At least one upper-tier alternating stack can be formed, and memory stack structures can be formed through the alternating stacks. A backside trench can be formed through the alternating stacks selective to the row of backside support pillar structures. The sacrificial material layers are replaced with electrically conductive layers, and the backside trench can be filled with a backside trench fill structure, which includes the row of backside support pillar structures. The row of backside support pillar structures reduces or prevents tilting or collapse of the alternating stacks during replacement of the sacrificial material layers with the electrically conductive layers.

公开(公告)号：US20190198515A1

公开(公告)日：2019-06-27

申请号：US15850073

申请日：2017-12-21

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Naohiro HOSODA ,  Keisuke SHIGEMURA ,  Junichi ARIYOSHI ,  Kazuki KAJITANI ,  Yuji FUKANO

IPC: H01L27/11556 ,  H01L27/11519 ,  H01L27/11565 ,  H01L27/11582 ,  H01L27/11524 ,  H01L27/1157 ,  H01L21/265 ,  H01L21/266

CPC classification number: H01L27/11556 ,  H01L21/26513 ,  H01L21/266 ,  H01L27/11519 ,  H01L27/11524 ,  H01L27/11565 ,  H01L27/1157 ,  H01L27/11582 ,  H01L29/408

Abstract: A memory device contains a stack of insulating layers and electrically conductive word line layers, at least one first drain select gate electrode located over the stack and extending through a first drain select transistor and a second drain select transistor, at least one second drain select gate electrode located between the first drain select electrode and the stack, and extending through a third drain select transistor and a fourth drain select transistor. The first drain select transistor and the third drain select transistor are located in a first NAND memory string. The second drain select transistor and the fourth drain select transistor are located in a second NAND memory string different from the first NAND memory string. The first drain select transistor has a higher threshold voltage than the second drain select transistor. The third drain select transistor has a lower threshold voltage than the fourth drain select transistor.