公开(公告)号：US20240074170A1

公开(公告)日：2024-02-29

申请号：US17823639

申请日：2022-08-31

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Takashi YUDA ,  Noriyuki NAGAHATA ,  Ippei YASUDA

IPC: H01L27/11556 ,  H01L27/11519 ,  H01L27/11524 ,  H01L27/11565 ,  H01L27/1157 ,  H01L27/11582

CPC classification number: H01L27/11556 ,  H01L27/11519 ,  H01L27/11524 ,  H01L27/11565 ,  H01L27/1157 ,  H01L27/11582

Abstract: A memory device includes an alternating stack of insulating layers and electrically conductive layers arranged along a vertical direction, a memory opening vertically extending through the alternating stack, and a memory opening fill structure located in the memory opening and including a vertical semiconductor channel and a memory film. The memory film includes a blocking dielectric film, a tunneling dielectric layer and a vertical stack of memory elements located between the blocking dielectric film and the tunneling dielectric layer. The blocking dielectric film includes component layers which include, from a side that is proximal to the vertical stack of memory elements toward a side that is distal from the vertical stack of memory elements, an inner silicon oxide blocking dielectric layer, a middle dielectric metal oxide blocking dielectric layer, an outer silicon oxide blocking dielectric layer, and an outer dielectric metal oxide blocking dielectric layer.

公开(公告)号：US20240147723A1

公开(公告)日：2024-05-02

申请号：US18351181

申请日：2023-07-12

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Motoo OHAGA ,  Tadashi NAKAMURA ,  Takashi YUDA ,  Nobuyuki FUJIMURA ,  Hiroyuki OGAWA

IPC: H10B43/27 ,  G11C16/04 ,  H01L23/522 ,  H01L23/528 ,  H10B41/10 ,  H10B41/27 ,  H10B41/35 ,  H10B43/10 ,  H10B43/35

CPC classification number: H10B43/27 ,  G11C16/0483 ,  H01L23/5226 ,  H01L23/5283 ,  H10B41/10 ,  H10B41/27 ,  H10B41/35 ,  H10B43/10 ,  H10B43/35

Abstract: A memory device includes source-level material layers including a source contact layer, an alternating stack of insulating layers and electrically conductive layers located over the source-level material layers, a memory opening vertically extending through the alternating stack and the source contact layer, and a memory opening fill structure located in the memory opening and including a vertical semiconductor channel including an intrinsic or first conductivity type semiconductor material, a memory film surrounding the vertical semiconductor channel, and a conical source pedestal in contact with the source contact layer and in contact with a bottom surface of the vertical semiconductor channel, such that at least portion of the conical source pedestal includes a second conductivity type semiconductor material.

公开(公告)号：US20200286909A1

公开(公告)日：2020-09-10

申请号：US16295206

申请日：2019-03-07

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Takashi YUDA ,  Hiroyuki KAMIYA

IPC: H01L27/11582 ,  H01L27/1157 ,  H01L27/11565 ,  H01L27/11573 ,  H01L21/28 ,  H01L21/02 ,  H01L21/306 ,  H01L23/522

Abstract: A three-dimensional memory device includes an alternating stack of insulating layers and electrically conductive layers located over a substrate, a memory opening extending through the alternating sack, and a memory opening fill structure located within the memory opening. The memory opening fill structure includes a pedestal channel portion, a memory film overlying the pedestal channel portion, a vertical semiconductor channel located inside the memory film, and a channel connection strap that extends through an opening of the memory film and contacting the pedestal channel portion and the vertical semiconductor channel. The channel connection strap has a topmost surface located below a horizontal plane including a top surface of the vertical semiconductor channel. The channel connection strap portion may be formed by a selective semiconductor growth from physically exposed semiconductor surfaces, and may provide enhanced electrical connection between the pedestal channel portion and the vertical semiconductor channel.

公开(公告)号：US20220109003A1

公开(公告)日：2022-04-07

申请号：US17064834

申请日：2020-10-07

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Noriyuki NAGAHATA ,  Takashi YUDA ,  Ryousuke ITOU

IPC: H01L27/11582

Abstract: A memory device includes an alternating stack of insulating layers and electrically conductive layers located over a substrate, a memory opening vertically extending through the alternating stack, and a memory opening fill structure located in the memory opening. The memory opening fill structure includes a memory film and a vertical semiconductor channel. The memory film includes a tunneling dielectric layer, a charge storage layer that laterally surrounds the tunneling dielectric layer, a dielectric metal oxide blocking dielectric layer that laterally surrounds the charge storage layer and contacts the vertical semiconductor channel, and a silicon oxide blocking dielectric layer that laterally surrounds the dielectric metal oxide blocking dielectric layer and contacts the vertical semiconductor channel.

公开(公告)号：US20200251485A1

公开(公告)日：2020-08-06

申请号：US16268132

申请日：2019-02-05

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Manabu KAKAZU ,  Takashi YUDA ,  Yuji FUKANO

IPC: H01L27/11582 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/1157 ,  H01L23/522 ,  H01L23/528 ,  H01L23/00 ,  H01L21/28 ,  H01L21/768

Abstract: A three-dimensional memory device includes a vertical semiconductor channel surrounding a vertical dielectric core. Laterally extending dielectric pegs structurally support the vertical semiconductor channel and the vertical dielectric core. The vertical semiconductor channel may be a single crystalline semiconductor channel.