公开(公告)号：US20250040165A1

公开(公告)日：2025-01-30

申请号：US18911058

申请日：2024-10-09

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Arnaud REGNIER ,  Dann MORILLON ,  Franck JULIEN ,  Marjorie HESSE

IPC: H01L29/66 ,  H01L21/28 ,  H01L21/8234 ,  H01L21/84 ,  H01L27/12 ,  H01L29/417 ,  H01L29/423 ,  H01L29/78 ,  H01L29/786

Abstract: A MOS transistor including a substrate, a conductive having lateral walls, drain and source regions, and spacers having an upper surface such that the spacers are buried in the substrate and are position between the conductive gate and the drain and source regions is provided. The spacers are each cuboid-shaped and have a width that is constant along the spacers height and independent from a height of the conductive gate. A device including the MOS transistor and a method of manufacture for producing a right-hand portion and a left-hand portion of a MOS transistor is also provided.

公开(公告)号：US20160308011A1

公开(公告)日：2016-10-20

申请号：US15195784

申请日：2016-06-28

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Francesco LA ROSA ,  Stephan NIEL ,  Julien DELALLEAU ,  Arnaud REGNIER

IPC: H01L29/423 ,  H01L27/115 ,  H01L29/66 ,  H01L21/28 ,  H01L21/306 ,  H01L29/788 ,  G11C16/14

CPC classification number: H01L29/42328 ,  G11C16/0425 ,  G11C16/14 ,  H01L21/28273 ,  H01L21/30604 ,  H01L21/32051 ,  H01L21/32133 ,  H01L27/11521 ,  H01L27/11524 ,  H01L29/42336 ,  H01L29/66666 ,  H01L29/66825 ,  H01L29/7827 ,  H01L29/788 ,  H01L29/7881 ,  H01L29/7883 ,  H01L29/7885

Abstract: The present disclosure relates to a memory cell comprising a vertical selection gate extending in a trench made in a substrate, a floating gate extending above the substrate, and a horizontal control gate extending above the floating gate, wherein the floating gate also extends above a portion of the vertical selection gate over a non-zero overlap distance. Application mainly to the production of a split gate memory cell programmable by hot-electron injection.

公开(公告)号：US20210175346A1

公开(公告)日：2021-06-10

申请号：US17180197

申请日：2021-02-19

Applicant: STMICROELECTRONICS (ROUSSET) SAS

Inventor： Arnaud REGNIER ,  Dann MORILLON ,  Franck JULIEN ,  Marjorie HESSE

IPC: H01L29/66 ,  H01L27/12 ,  H01L29/423 ,  H01L21/8234 ,  H01L29/786 ,  H01L29/417 ,  H01L21/28 ,  H01L21/84 ,  H01L29/78

Abstract: A method of manufacturing a MOS transistor includes forming a conductive first gate and forming insulating spacers along opposite sides of the gate, wherein the spacers are formed before the gate.

公开(公告)号：US20210057329A1

公开(公告)日：2021-02-25

申请号：US16546569

申请日：2019-08-21

Applicant: STMicroelectronics (Rousset) SAS ,  STMicroelectronics (Crolles 2) SAS

Inventor： Abderrezak MARZAKI ,  Arnaud REGNIER ,  Stephan NIEL

IPC: H01L23/522 ,  H01L27/11524 ,  H01L49/02

Abstract: First and second wells are formed in a semiconductor substrate. First and second trenches in the first second wells, respectively, each extend vertically and include a central conductor insulated by a first insulating layer. A second insulating layer is formed on a top surface of the semiconductor substrate. The second insulating layer is selectively thinned over the second trench. A polysilicon layer is deposited on the second insulating layer and then lithographically patterned to form: a first polysilicon portion over the first well that is electrically connected to the central conductor of the first trench to form a first capacitor plate, a second capacitor plate formed by the first well; and a second polysilicon portion over the second well forming a floating gate electrode of a floating gate transistor of a memory cell having an access transistor whose control gate is formed by the central conductor of the second trench.

公开(公告)号：US20150236031A1

公开(公告)日：2015-08-20

申请号：US14625356

申请日：2015-02-18

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Marc MANTELLI ,  Stephan NIEL ,  Arnaud REGNIER ,  Francesco LA ROSA ,  Julien DELALLEAU

IPC: H01L27/115 ,  H01L29/788 ,  G11C16/14 ,  H01L21/3213 ,  H01L21/306 ,  H01L21/308 ,  H01L21/266 ,  H01L29/423 ,  H01L21/28

CPC classification number: H01L29/7883 ,  G11C16/0425 ,  G11C16/14 ,  H01L21/266 ,  H01L21/28273 ,  H01L21/30604 ,  H01L21/308 ,  H01L21/32133 ,  H01L27/11521 ,  H01L27/11524 ,  H01L27/11553 ,  H01L27/11556 ,  H01L29/42328 ,  H01L29/42336 ,  H01L29/66666 ,  H01L29/66825 ,  H01L29/788

Abstract: The present disclosure relates to a memory cell that includes a vertical selection gate, a floating gate extending above the substrate, wherein the floating gate also extends above a portion of the vertical selection gate, over a non-zero overlap distance, the memory cell comprising a doped region implanted at the intersection of a vertical channel region extending opposite the selection gate and a horizontal channel region extending opposite the floating gate.

Abstract translation: 本公开涉及一种存储单元，其包括垂直选择栅极，在衬底上方延伸的浮置栅极，其中浮置栅极还在非零重叠距离上延伸到垂直选择栅极的一部分上方，存储器单元包括 注入在与选择栅极相对延伸的垂直沟道区域的相交处的掺杂区域和与浮动栅极相对延伸的水平沟道区域。

公开(公告)号：US20190207014A1

公开(公告)日：2019-07-04

申请号：US16228032

申请日：2018-12-20

Applicant: STMICROELECTRONICS (ROUSSET) SAS

Inventor： Arnaud REGNIER ,  Dann MORILLON ,  Franck JULIEN ,  Marjorie HESSE

IPC: H01L29/66 ,  H01L21/28 ,  H01L21/84 ,  H01L27/12 ,  H01L29/423

CPC classification number: H01L29/66568 ,  H01L21/28114 ,  H01L21/28132 ,  H01L21/823468 ,  H01L21/84 ,  H01L27/1207 ,  H01L29/41775 ,  H01L29/42372 ,  H01L29/42376 ,  H01L29/6656 ,  H01L29/66659 ,  H01L29/7833 ,  H01L29/78654

Abstract: A method of manufacturing a MOS transistor includes forming a conductive first gate and forming insulating spacers along opposite sides of the gate, wherein the spacers are formed before the gate.

公开(公告)号：US20190067291A1

公开(公告)日：2019-02-28

申请号：US16111480

申请日：2018-08-24

Applicant: STMicroelectronics (Rousset) SAS ,  STMicroelectronics (Crolles 2) SAS

Inventor： Abderrezak MARZAKI ,  Arnaud REGNIER ,  Stephan NIEL ,  Quentin HUBERT ,  Thomas CABOUT

IPC: H01L27/108 ,  H01L29/66 ,  H01L49/02

CPC classification number: H01L27/10841 ,  H01L27/10864 ,  H01L27/10867 ,  H01L27/1087 ,  H01L27/10876 ,  H01L28/60 ,  H01L29/66181 ,  H01L29/945

Abstract: A capacitive element includes a trench extending vertically into a well from a first side. The trench is filled with a conductive central section clad with an insulating cladding. The capacitive element further includes a first conductive layer covering a first insulating layer that is located on the first side and a second conductive layer covering a second insulating layer that is located on the first conductive layer. The conductive central section and the first conductive layer are electrically connected to form a first electrode of the capacitive element. The second conductive layer and the well are electrically connected to form a second electrode of the capacitive element. The insulating cladding, the first insulating layer and the second insulating layer form a dielectric region of the capacitive element.

公开(公告)号：US20170084749A1

公开(公告)日：2017-03-23

申请号：US15365768

申请日：2016-11-30

Applicant: STMICROELECTRONICS (ROUSSET) SAS

Inventor： Marc MANTELLI ,  Stephan NIEL ,  Arnaud REGNIER ,  Francesco LA ROSA ,  Julien DELALLEAU

IPC: H01L29/788 ,  G11C16/04 ,  H01L27/115 ,  H01L21/28 ,  H01L29/423 ,  H01L29/66

CPC classification number: H01L29/7883 ,  G11C16/0425 ,  G11C16/14 ,  H01L21/266 ,  H01L21/28273 ,  H01L21/30604 ,  H01L21/308 ,  H01L21/32133 ,  H01L27/11521 ,  H01L27/11524 ,  H01L27/11553 ,  H01L27/11556 ,  H01L29/42328 ,  H01L29/42336 ,  H01L29/66666 ,  H01L29/66825 ,  H01L29/788

Abstract: Various embodiments provide a memory cell that includes a vertical selection gate, a floating gate extending above the substrate, wherein the floating gate also extends above a portion of the vertical selection gate, over a non-zero overlap distance, the memory cell comprising a doped region implanted at the intersection of a vertical channel region extending opposite the selection gate and a horizontal channel region extending opposite the floating gate.

公开(公告)号：US20210225757A1

公开(公告)日：2021-07-22

申请号：US17226324

申请日：2021-04-09

Applicant: STMicroelectronics (Rousset) SAS ,  STMicroelectronics (Crolles 2) SAS

Inventor： Abderrezak MARZAKI ,  Arnaud REGNIER ,  Stephan NIEL

IPC: H01L23/522 ,  H01L49/02 ,  H01L27/11524

Abstract: First and second wells are formed in a semiconductor substrate. First and second trenches in the first second wells, respectively, each extend vertically and include a central conductor insulated by a first insulating layer. A second insulating layer is formed on a top surface of the semiconductor substrate. The second insulating layer is selectively thinned over the second trench. A polysilicon layer is deposited on the second insulating layer and then lithographically patterned to form: a first polysilicon portion over the first well that is electrically connected to the central conductor of the first trench to form a first capacitor plate, a second capacitor plate formed by the first well; and a second polysilicon portion over the second well forming a floating gate electrode of a floating gate transistor of a memory cell having an access transistor whose control gate is formed by the central conductor of the second trench.

公开(公告)号：US20210005613A1

公开(公告)日：2021-01-07

申请号：US17026874

申请日：2020-09-21

Applicant: STMicroelectronics (Rousset) SAS ,  STMicroelectronics (Crolles 2) SAS

Inventor： Abderrezak MARZAKI ,  Arnaud REGNIER ,  Stephan NIEL ,  Quentin HUBERT ,  Thomas CABOUT

IPC: H01L27/108 ,  H01L29/66 ,  H01L49/02 ,  H01L29/94

Abstract: A capacitive element includes a trench extending vertically into a well from a first side. The trench is filled with a conductive central section clad with an insulating cladding. The capacitive element further includes a first conductive layer covering a first insulating layer that is located on the first side and a second conductive layer covering a second insulating layer that is located on the first conductive layer. The conductive central section and the first conductive layer are electrically connected to form a first electrode of the capacitive element. The second conductive layer and the well are electrically connected to form a second electrode of the capacitive element. The insulating cladding, the first insulating layer and the second insulating layer form a dielectric region of the capacitive element.