公开(公告)号：US20170117296A1

公开(公告)日：2017-04-27

申请号：US15296205

申请日：2016-10-18

Applicant: STMicroelectronics (Crolles 2) SAS ,  Commissariat A L'Energie Atomique et aux Energies Alternatives

Inventor： Sonarith Chhun ,  Emmanuel Josse ,  Gregory Bidal ,  Dominique Golanski ,  Francois Andrieu ,  Jerome Mazurier ,  Olivier Weber

IPC: H01L27/12 ,  H01L29/66 ,  H01L21/306 ,  H01L21/8234 ,  H01L21/02 ,  H01L27/092 ,  H01L29/08 ,  H01L29/417 ,  H01L21/8238 ,  H01L21/84

CPC classification number: H01L27/1203 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/02529 ,  H01L21/02532 ,  H01L21/30608 ,  H01L21/823418 ,  H01L21/823437 ,  H01L21/823468 ,  H01L21/823814 ,  H01L21/823828 ,  H01L21/823864 ,  H01L21/84 ,  H01L27/0922 ,  H01L29/0847 ,  H01L29/16 ,  H01L29/1608 ,  H01L29/161 ,  H01L29/41783 ,  H01L29/6653

Abstract: A device includes both low-voltage (LV) and high-voltage (HV) metal oxide semiconductor (MOS) transistors of opposite types. Gate stacks for the transistors are formed over a semiconductor layer. First spacers made of a first insulator are provided on the gate stacks of the LV and HV MOS transistors. Second spacers made of a second insulator are provided on the gate stacks of the HV MOS transistors only. The insulators are selectively removed to expose the semiconductor layer. Epitaxial growth of semiconductor material is made from the exposed semiconductor layer to form raised source-drain structures that are separated from the gate stacks by the first spacers for the LV MOS transistors and the second spacers for the HV MOS transistors.

公开(公告)号：US11581449B2

公开(公告)日：2023-02-14

申请号：US16703689

申请日：2019-12-04

Applicant: STMicroelectronics (Crolles 2) SAS

Inventor： Younes Benhammou ,  Dominique Golanski ,  Denis Rideau

IPC: H01L31/107 ,  H01L31/028 ,  H01L31/0745 ,  H01L31/18

Abstract: The present disclosure relates to a photodiode comprising a first part made of silicon and a second part made of doped germanium lying on and in contact with the first part, the first part comprising a stack of a first area and of a second area forming a p-n junction and the doping level of the germanium increasing as the distance from the p-n junction increases.

公开(公告)号：US20170317106A1

公开(公告)日：2017-11-02

申请号：US15361937

申请日：2016-11-28

Applicant: STMicroelectronics (Rousset) SAS ,  STMicroelectronics (Crolles 2) SAS

Inventor： Philippe Boivin ,  Franck Arnaud ,  Gregory Bidal ,  Dominique Golanski ,  Emmanuel Richard

IPC: H01L27/12 ,  H01L29/06 ,  H01L29/08 ,  H01L29/49

CPC classification number: H01L27/1207 ,  H01L29/0653 ,  H01L29/0847 ,  H01L29/4916

Abstract: An integrated circuit is formed using a substrate of a silicon-on-insulator type that includes a carrier substrate and a stack of a buried insulating layer and a semiconductor film on the carrier substrate. A first region without the stack separates a second region that includes the stack from a third region that also includes the stack. An MOS transistor has a gate dielectric region formed by a portion of the buried insulating layer in the second region and a gate region formed by a portion of the semiconductor film in the second region. The carrier substrate incorporates doped regions under the first region which form at least a part of a source region and drain region of the MOS transistor.

公开(公告)号：US11949035B2

公开(公告)日：2024-04-02

申请号：US17546503

申请日：2021-12-09

Applicant: STMicroelectronics (Crolles 2) SAS ,  STMicroelectronics (Research & Development) Limited

Inventor： Denis Rideau ,  Dominique Golanski ,  Alexandre Lopez ,  Gabriel Mugny

IPC: H01L31/107 ,  H01L31/18

CPC classification number: H01L31/107 ,  H01L31/186

Abstract: A single photon avalanche diode (SPAD) includes a PN junction in a semiconductor well doped with a first type of dopant. The PN junction is formed between a first region doped with the first type of dopant and a second region doped with a second type of dopant opposite to the first type of dopant. The first doped region is shaped so as to incorporate local variations in concentration of dopants that are configured, in response to a voltage between the second doped region and the semiconductor well that is greater than or equal to a level of a breakdown voltage of the PN junction, to generate a monotonic variation in the electrostatic potential between the first doped region and the semiconductor well.

公开(公告)号：US09786755B2

公开(公告)日：2017-10-10

申请号：US14930150

申请日：2015-11-02

Applicant: STMicroelectronics (Crolles 2) SAS

Inventor： Dominique Golanski ,  Gregory Bidal ,  Simon Jeannot

IPC: H01L21/84 ,  H01L29/423 ,  H01L27/12 ,  H01L29/06 ,  H01L29/08 ,  H01L29/66 ,  H01L29/78 ,  H01L29/788

CPC classification number: H01L29/42364 ,  H01L27/12 ,  H01L27/1207 ,  H01L29/0649 ,  H01L29/0847 ,  H01L29/66545 ,  H01L29/7838 ,  H01L29/7881

Abstract: An integrated circuit includes a first zone for a first transistor and a second zone for a second transistor. The transistors are supported by a substrate of the silicon-on-insulator type that includes a semiconductor film on a buried insulating layer on a carrier substrate. In the second zone, the semiconductor film has been removed. The second transistor in the second zone includes a gate-dielectric region resting on the carrier substrate that is formed by a portion of the buried insulating layer). The first transistor in the first zone includes a gate-dielectric region formed by a dielectric layer on the semiconductor film.

公开(公告)号：US12087873B2

公开(公告)日：2024-09-10

申请号：US17702186

申请日：2022-03-23

Applicant: STMicroelectronics (Crolles 2) SAS

Inventor： Antonin Zimmer ,  Dominique Golanski ,  Raul Andres Bianchi

IPC: H01L31/107

CPC classification number: H01L31/107

Abstract: A photodiode is formed in a semiconductor substrate of a first conductivity type. The photodiode includes a first region having a substantially hemispherical shape and a substantially hemispherical core of a second conductivity type, different from the first conductivity type, within the first region. An epitaxial layer covers the semiconductor substrate and buries the first region and core.

公开(公告)号：US09876032B2

公开(公告)日：2018-01-23

申请号：US15296205

申请日：2016-10-18

Applicant: STMicroelectronics (Crolles 2) SAS ,  Commissariat A L'Energie Atomique et aux Energies Alternatives

Inventor： Sonarith Chhun ,  Emmanuel Josse ,  Gregory Bidal ,  Dominique Golanski ,  Francois Andrieu ,  Jerome Mazurier ,  Olivier Weber

IPC: H01L21/336 ,  H01L27/092 ,  H01L27/12 ,  H01L21/8238 ,  H01L29/66 ,  H01L21/306 ,  H01L21/84 ,  H01L21/02 ,  H01L29/08 ,  H01L29/417 ,  H01L21/8234 ,  H01L29/16 ,  H01L29/161

CPC classification number: H01L27/1203 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/02529 ,  H01L21/02532 ,  H01L21/30608 ,  H01L21/823418 ,  H01L21/823437 ,  H01L21/823468 ,  H01L21/823814 ,  H01L21/823828 ,  H01L21/823864 ,  H01L21/84 ,  H01L27/0922 ,  H01L29/0847 ,  H01L29/16 ,  H01L29/1608 ,  H01L29/161 ,  H01L29/41783 ,  H01L29/6653

Abstract: A device includes both low-voltage (LV) and high-voltage (HV) metal oxide semiconductor (MOS) transistors of opposite types. Gate stacks for the transistors are formed over a semiconductor layer. First spacers made of a first insulator are provided on the gate stacks of the LV and HV MOS transistors. Second spacers made of a second insulator are provided on the gate stacks of the HV MOS transistors only. The insulators are selectively removed to expose the semiconductor layer. Epitaxial growth of semiconductor material is made from the exposed semiconductor layer to form raised source-drain structures that are separated from the gate stacks by the first spacers for the LV MOS transistors and the second spacers for the HV MOS transistors.

公开(公告)号：US20160276451A1

公开(公告)日：2016-09-22

申请号：US14930150

申请日：2015-11-02

Applicant: STMicroelectronics (Crolles 2) SAS

Inventor： Dominique Golanski ,  Gregory Bidal ,  Simon Jeannot

IPC: H01L29/423 ,  H01L29/06 ,  H01L29/08 ,  H01L29/788 ,  H01L29/66 ,  H01L27/12 ,  H01L29/78

CPC classification number: H01L29/42364 ,  H01L27/12 ,  H01L27/1207 ,  H01L29/0649 ,  H01L29/0847 ,  H01L29/66545 ,  H01L29/7838 ,  H01L29/7881

Abstract: An integrated circuit includes a first zone for a first transistor and a second zone for a second transistor. The transistors are supported by a substrate of the silicon-on-insulator type that includes a semiconductor film on a buried insulating layer on a carrier substrate. In the second zone, the semiconductor film has been removed. The second transistor in the second zone includes a gate-dielectric region resting on the carrier substrate that is formed by a portion of the buried insulating layer). The first transistor in the first zone includes a gate-dielectric region formed by a dielectric layer on the semiconductor film.

Abstract translation: 集成电路包括用于第一晶体管的第一区和用于第二晶体管的第二区。 晶体管由绝缘体上的类型的衬底支撑，其中包括在载体衬底上的掩埋绝缘层上的半导体膜。 在第二区域中，已经去除了半导体膜。 第二区域中的第二晶体管包括搁置在由掩埋绝缘层的一部分形成的载体衬底上的栅极介电区域）。 第一区域中的第一晶体管包括由半导体膜上的电介质层形成的栅介电区域。