-
公开(公告)号：US20240039545A1
公开(公告)日：2024-02-01
申请号：US18348899
申请日：2023-07-07
Applicant: STMicroelectronics International N.V.
Inventor： Rupesh SINGH , Ankur BAL
CPC classification number: H03L7/195 , H03L7/199 , H03K3/356026
Abstract: Provided are a method and apparatus for controlling a skew between multiple data lanes. In the method and apparatus, a first data lane control stage controls control outputting first data over a first data lane based on a first data lane clock and a second data lane control stage controls outputting second data over a second data lane based on a second data lane clock. In the method and apparatus, a first device is associated with a system clock and is configured to generate the first and second data for outputting over the first and second data lanes. A clock control stage causes the first and second data lane clocks to be offset from each other by a fixed time duration that is an integer fraction of a cycle duration of the system clock.
-
公开(公告)号：US20210343319A1
公开(公告)日：2021-11-04
申请号：US17374304
申请日：2021-07-13
Applicant: STMicroelectronics International N.V.
Inventor： Ankur BAL , Rupesh SINGH , Vivek TRIPATHI
Abstract: A quantizer generates a thermometer coded signal from an analog voltage signal. Data weighted averaging (DWA) of the thermometer coded signal is accomplished by controlling the operation of a crossbar switch controlled by a switch control signal to generate an output DWA signal. The output DWA signal is latched to generate a latched output DWA signal which is processed along with bits of the thermometer coded input signal in feedback loop to generate the switch control signal. The latching of the output DWA signal is performed in an input register of a digital-to-analog converter which operates to convert the latched output DWA signal to a feedback analog voltage from which the analog voltage signal is generated. The switch control signal specifies a bit location for a beginning logic transition of the output DWA signal cycle based on detection of an ending logic transition of the latched DWA signal.
-
公开(公告)号：US20240364347A1
公开(公告)日：2024-10-31
申请号：US18623331
申请日：2024-04-01
Applicant: STMicroelectronics International N.V.
Inventor： Rupesh SINGH , Ankur BAL , Kirtiman Singh RATHORE
IPC: H03L7/00 , H03K3/037 , H03K5/1534 , H03K19/20
CPC classification number: H03L7/00 , H03K3/037 , H03K5/1534 , H03K19/20
Abstract: A first latching circuit has a reset function controlled by a reset signal and configured to latch a logic state in response to a first edge of a clock signal to generate a first output signal. A second latching circuit has a reset function controlled by that reset signal and configured to latch a logic state in response to a second edge of that clock signal to generate a second output signal. The first and second edges are opposite edges. A combinatorial logic circuit logically combines the first and second output signals to generate a logic output signal. A third latching circuit has a reset function controlled by that reset signal and configured to latch the logic output signal in response to the second edge of that clock signal to generate a reset synchronization control signal.
-
4.发明申请公开(公告)号：US20220188203A1
公开(公告)日：2022-06-16
申请号：US17682167
申请日：2022-02-28
Applicant: STMicroelectronics International N.V.
Inventor： Ankur BAL , Rupesh SINGH
Abstract: A serial-connection is tested by transmitting a PRBS generated using a kth-order monic-polynomial from transmission-circuitry to reception-circuitry, and determining operation is proper based upon the PRBS received. The PRBS is formed by generating x intermediate-words of the PRBS, x being a result of an integer-divide between a total number of bits in the PRBS and a bit-width of a serializer that transmits the PRBS, generating a leading-word of the PRBS as having first y-bits of the PRBS as its LSBs, y being based upon a modulo-divide between the total number of bits in the PRBS and x, and generating a trailing-word of the PRBS as having last z-bits of the PRBS as its MSBs, z being based upon a difference between a result of the modulo-divide and y. The PRBS is transmitted sequentially as the leading-word of the PRBS, the intermediate-words of the PRBS, and the trailing-word of the PRBS.
-
公开(公告)号：US20230251829A1
公开(公告)日：2023-08-10
申请号：US18134737
申请日：2023-04-14
Applicant: STMicroelectronics International N.V.
Inventor： Ankur BAL , Rupesh SINGH
CPC classification number: G06F7/548 , H03K3/037 , G06F7/5443 , H03K5/01 , H03K2005/00078
Abstract: A first multiplier multiplies a first input with a first coefficient and a first adder sums an output of the first multiplier and a second input to generate a first output. A second multiplier multiplies a third input with a second coefficient, a third multiplier multiplies a fourth input with a third coefficient, and a second adder sums outputs of the second and third multipliers to generate a second output. The second and third inputs are derived from the first output and the first and fourth inputs are derived from the second output. The first and second outputs generate digital values for first and second digital sinusoids, respectively.
-
Patent Agency Ranking
公开(公告)号：US20220069837A1
公开(公告)日：2022-03-03
申请号：US17374351
申请日：2021-07-13
Applicant: STMicroelectronics International N.V.
Inventor： Ankur BAL , Rupesh SINGH
Abstract: A latch circuit sequentially latches a first data weighted averaging (DWA) data word and then a second DWA data word. A first detector circuit identifies a first bit location in the first DWA data that is associated with an ending of a first string of logic 1 bits in the first DWA data word. A second detector circuit identifies a second bit location in the second DWA data word associated with an ending of a second string of logic 1 bits in the second DWA data word. A DWA-to-binary conversion circuit converts the second DWA data word to a binary word by using the first bit location and second bit location to identify a number of logic 1 bits present in said second DWA data word. A binary value for that binary word that is equal to the identified number is output.
-
公开(公告)号：US20210081174A1
公开(公告)日：2021-03-18
申请号：US16988912
申请日：2020-08-10
Applicant: STMicroelectronics International N.V.
Inventor： Ankur BAL , Rupesh SINGH
Abstract: A first multiplier multiplies a first input with a first coefficient and a first adder sums an output of the first multiplier and a second input to generate a first output. A second multiplier multiplies a third input with a second coefficient, a third multiplier multiplies a fourth input with a third coefficient, and a second adder sums outputs of the second and third multipliers to generate a second output. The second and third inputs are derived from the first output and the first and fourth inputs are derived from the second output. The first and second outputs generate digital values for first and second digital sinusoids, respectively.
-
公开(公告)号：US20230033569A1
公开(公告)日：2023-02-02
申请号：US17867496
申请日：2022-07-18
Applicant: STMicroelectronics International N.V.
Inventor： Ankur BAL , Rupesh SINGH
IPC: H03H17/02
Abstract: A finite impulse response (FIR) filter includes a plurality of registers. The data input terminal of each register is directly coupled to the input of the FIR filter. A new data value is passed to each register on each clock cycle of a filter clock signal. Only one of the registers processes the data value on each clock cycle. A ring counter is coupled to the registers and determines which register processes the data value on each dock cycle.
-
9.发明申请公开(公告)号：US20220006467A1
公开(公告)日：2022-01-06
申请号：US17342416
申请日：2021-06-08
Applicant: STMICROELECTRONICS INTERNATIONAL N.V.
Inventor： Ankur BAL , Sri Ram GUPTA , Rupesh SINGH
Abstract: An integrated circuit includes a successive approximation register (SAR) analog-to-digital converter (ADC). The ADC includes a bit step selector. During testing of the ADC, the bit step selector selects a number of bits to be tested for a next analog test voltage based on digital values that are within an integer delta value of most recent digital value for a most recent analog test voltage.
-
10.发明申请公开(公告)号：US20200186162A1
公开(公告)日：2020-06-11
申请号：US16702246
申请日：2019-12-03
Applicant: STMicroelectronics International N.V.
Inventor： Ankur BAL , Rupesh SINGH
Abstract: A continuous time Delta-Sigma (CT-ΔΣ) modulator has an input node configured to receive an input signal and an output node configured to output a digital output signal. The CT-ΔΣ modulator includes a feedback loop with a summation circuit configured to sum the digital output signal with a jitter perturbed test signal to generate a signal supplied to an input of a digital to analog converter circuit. A single tone signal is injected with a jitter error of a clock signal to generate the jitter perturbed test signal. A processing circuit processes the digital output signal to detect a signal to noise ratio of the CT-ΔΣ modulator. The detected signal to noise ratio is indicative of presence of jitter in the clock signal.
-
-
-
-
-
-
-
-
-
Search Results
16
records
(took 0.012 seconds)
