公开(公告)号：US11521697B2

公开(公告)日：2022-12-06

申请号：US16742292

申请日：2020-01-14

Applicant: STMicroelectronics International N.V.

Inventor： Shishir Kumar ,  Abhishek Pathak

IPC: G11C29/38 ,  G11C29/44 ,  G11C8/10

Abstract: A row decoder located on one side of a memory array selectively drives word lines in response to a row address. A word line fault detection circuit located on an opposite side of the first memory array operates to detect an open word line fault between the opposed sides of the memory array. The word line fault detection circuit includes a first clamp circuit that operates to clamp the word lines to ground. An encoder circuit encodes signals on the word lines to generate an encoded address. The encoded address is compared to the row address by a comparator circuit which sets an error flag indicating the open word line fault has been detected if the encoded address does not match the row address.

公开(公告)号：US11152376B2

公开(公告)日：2021-10-19

申请号：US16211113

申请日：2018-12-05

Applicant: STMicroelectronics International N.V.

Inventor： Tushar Sharma ,  Tanmoy Roy ,  Shishir Kumar

IPC: G11C5/06 ,  H01L27/11 ,  G11C11/412 ,  H01L27/02 ,  G11C8/16 ,  G11C11/417

Abstract: The present disclosure is directed to a circuit layout of a dual port static random-access-memory (SRAM) cell. The memory cell includes active regions in a substrate, with polysilicon gate electrodes on the active regions to define transistors of the memory cell. The eight transistor (8T) memory cell layout includes a reduced aspect ratio and non-polysilicon bit line discharge path routing by positioning an active region for the first port opposite an active region for the second port and consolidating power line nodes at a central portion of the memory cell.

公开(公告)号：US10998077B2

公开(公告)日：2021-05-04

申请号：US16702744

申请日：2019-12-04

Applicant: STMicroelectronics International N.V.

Inventor： Rohit Bhasin ,  Shishir Kumar ,  Tanmoy Roy ,  Deepak Kumar Bihani

IPC: G11C29/38 ,  G11C29/14

Abstract: A decoder decodes a memory address and selectively drives a select line (such as a word line or mux line) of a memory. An encoding circuit encodes the data on select lines to generate an encoded address. The encoded address and the memory address are compared by a comparison circuit to generate a test result signal which is indicative of whether the decoder is operating properly. To test the comparison circuit for proper operation, a subset of an MBIST scan routine causes the encoded address to be blocked from the comparison circuit and a force signal to be applied in its place. A test signal from the scan routine and the force signal are then compared by the comparison circuit, with the test result signal generated from the comparison being indicative of whether the comparison circuit itself is operating properly.

公开(公告)号：US11532633B2

公开(公告)日：2022-12-20

申请号：US17491201

申请日：2021-09-30

Applicant: STMICROELECTRONICS INTERNATIONAL N.V.

Inventor： Tushar Sharma ,  Tanmoy Roy ,  Shishir Kumar

IPC: G11C11/00 ,  H01L27/11 ,  G11C5/06 ,  G11C11/412 ,  H01L27/02 ,  G11C8/16 ,  G11C11/417

Abstract: The present disclosure is directed to a circuit layout of a dual port static random-access-memory (SRAM) cell. The memory cell includes active regions in a substrate, with polysilicon gate electrodes on the active regions to define transistors of the memory cell. The eight transistor (8T) memory cell layout includes a reduced aspect ratio and non-polysilicon bit line discharge path routing by positioning an active region for the first port opposite an active region for the second port and consolidating power line nodes at a central portion of the memory cell.

公开(公告)号：US11025252B2

公开(公告)日：2021-06-01

申请号：US16578487

申请日：2019-09-23

Applicant: STMicroelectronics International N.V.

Inventor： Shishir Kumar ,  Tanuj Kumar ,  Deepak Kumar Bihani

IPC: H03K19/003

Abstract: A failure determination circuit includes a latch circuit that receives an internal clock from a clock latch that rises in response to an external clock rising. In response to a rising edge of the external clock, the circuit generates a rising edge of a fault flag. In response to a rising edge of the internal clock if it occurs, the fault flag falls. The fault flag is then latched. The latched fault flag indicates a single bit upset in the clock latch if the falling edge of the fault flag was not generated prior to latching, if the clock latch is in an active mode, and indicates a single bit upset in the clock latch if the falling edge of the fault flag was generated prior to latching, if the clock latch is in an inactive mode.

公开(公告)号：US10706915B2

公开(公告)日：2020-07-07

申请号：US16351773

申请日：2019-03-13

Applicant: STMicroelectronics International N.V.

Inventor： Abhishek Pathak ,  Tanmoy Roy ,  Shishir Kumar

IPC: G11C7/00 ,  G11C11/412 ,  G11C7/14 ,  G11C11/419 ,  G11C8/08 ,  G11C11/413 ,  G11C11/418

Abstract: A memory device includes first and second dummy word line portions. A dummy word line driver drives the first dummy word line portion. A voltage dropping circuit causes a voltage on the second dummy word line to be less than a voltage on the first dummy word line. At least one dummy memory cell is coupled to the second dummy word line portion, remains in standby until assertion of the second dummy word line, and performs a dummy cycle in response to assertion of the second dummy word line. A reset signal generation circuit generates a reset signal in response to completion of a dummy cycle by the at least one dummy memory cell. An internal clock signal is generated from an external clock signal and the reset signal and is used in performing a read and/or write cycle to a memory array.

公开(公告)号：US20150365080A1

公开(公告)日：2015-12-17

申请号：US14304357

申请日：2014-06-13

Applicant: STMicroelectronics International N.V.

Inventor： Shishir Kumar ,  Tanmoy Roy

IPC: H03K5/01 ,  G11C8/18

CPC classification number: H03K5/01 ,  G11C7/222 ,  G11C8/18

Abstract: According to an embodiment, a method of generating a clock pulse includes receiving a leading edge at a clock input at a time when an enable signal is active, generating an edge at a clock output based on the received leading edge at the clock input, latching a logic value corresponding to the edge at the clock output, preventing changes at the clock input from affecting the latched logic value after the logic value is latched, resetting the latched logic value after a first delay time, and maintaining the reset logic value until a second edge is received at the clock input. The second edge at the clock input matches the leading edge at the clock input.

Abstract translation: 根据实施例，一种产生时钟脉冲的方法包括在使能信号有效时在时钟输入端处接收前沿，在时钟输出端基于接收到的前沿产生时钟输出的边沿，锁存 对应于时钟输出端的逻辑值，防止在逻辑值被锁存之后时钟输入的变化影响锁存的逻辑值，在第一延迟时间之后复位锁存的逻辑值，并保持复位逻辑值直到 在时钟输入端接收第二个边沿。 时钟输入端的第二个边沿与时钟输入端的前沿匹配。

公开(公告)号：US11195576B2

公开(公告)日：2021-12-07

申请号：US16596989

申请日：2019-10-09

Applicant: STMicroelectronics International N.V.

Inventor： Shishir Kumar ,  Bhupender Singh

IPC: G11C11/419 ,  G11C11/417

Abstract: A sense amplifier enable signal and a tracking signal are generated in response to an indication that a sufficient voltage difference has developed across bit lines of a memory. The sense amplifier enable signal has a pulse width between a leading edge and a trailing edge. The sense amplifier enable signal is propagated along a first U-turn signal line that extends parallel to rows of the memory array and is coupled to sense amplifiers arranged in a row to generate a sense amplifier enable return signal. The tracking signal is propagated along a second U-turn signal line extending parallel to columns of the memory array to generate a tracking return signal. The sense amplifier enable return signal and the tracking return signal are logically combined to generate a reset signal. Timing of the trailing edge of the pulse width is controlled by the reset signal.

公开(公告)号：US10311944B2

公开(公告)日：2019-06-04

申请号：US16025647

申请日：2018-07-02

Applicant: STMicroelectronics International N.V.

Inventor： Dhori Kedar Janardan ,  Abhishek Pathak ,  Shishir Kumar

IPC: G11C5/06 ,  G11C11/417

Abstract: A first transistor has a first conduction terminal coupled to a second bit line, a second conduction terminal coupled to a bit line node, and a control terminal biased by a second control signal. A second transistor has a first conduction terminal coupled to a second complementary bit line, a second conduction terminal coupled to a complementary bit line node, and a control terminal biased by the second control signal. A first replica transistor has a first conduction terminal coupled to the second bit line, a second conduction terminal coupled to the complementary bit line node, and a control terminal biased such that the first replica transistor is off. A second replica transistor has a first conduction terminal coupled to the second complementary bit line, a second conduction terminal coupled to the bit line node, and a control terminal biased such that the second replica transistor is off.

公开(公告)号：US09590602B2

公开(公告)日：2017-03-07

申请号：US14304357

申请日：2014-06-13

Applicant: STMicroelectronics International N.V.

Inventor： Shishir Kumar ,  Tanmoy Roy

IPC: H03K5/01 ,  G11C8/18 ,  G11C7/22

CPC classification number: H03K5/01 ,  G11C7/222 ,  G11C8/18

Abstract: According to an embodiment, a method of generating a clock pulse includes receiving a leading edge at a clock input at a time when an enable signal is active, generating an edge at a clock output based on the received leading edge at the clock input, latching a logic value corresponding to the edge at the clock output, preventing changes at the clock input from affecting the latched logic value after the logic value is latched, resetting the latched logic value after a first delay time, and maintaining the reset logic value until a second edge is received at the clock input. The second edge at the clock input matches the leading edge at the clock input.

Abstract translation: 根据实施例，一种产生时钟脉冲的方法包括在使能信号有效时在时钟输入端处接收前沿，在时钟输出端基于接收到的前沿产生时钟输出的边沿，锁存 对应于时钟输出端的逻辑值，防止在逻辑值被锁存之后时钟输入的变化影响锁存的逻辑值，在第一延迟时间之后复位锁存的逻辑值，并保持复位逻辑值直到 在时钟输入端接收第二个边沿。 时钟输入端的第二个边沿与时钟输入端的前沿匹配。