公开(公告)号：US12032460B2

公开(公告)日：2024-07-09

申请号：US17670055

申请日：2022-02-11

Applicant: STMicroelectronics S.r.l.

Inventor： Enea Dimroci ,  Francesca Giacoma Mignemi ,  Roberta Priolo ,  Marco Leo ,  Francesco Battini

IPC: G06F11/273 ,  G06F11/26

CPC classification number: G06F11/26 ,  G06F11/273

Abstract: A method to test an asynchronous finite state machine for faults, the method including disabling state transitions out of a state of the asynchronous finite state machine and inputting test data to the AFSM to trigger a transition from the state to an expected state. The method further including enabling transitions out of the state of the asynchronous finite state machine, and determining whether the asynchronous finite state machine has performed a successful transition to the expected state.

公开(公告)号：US10204066B2

公开(公告)日：2019-02-12

申请号：US15363932

申请日：2016-11-29

Applicant: STMICROELECTRONICS S.R.L.

Inventor： Eugenio Miluzzi ,  Marco Leo ,  Marco Castellano

IPC: G06F13/12 ,  G06F13/364 ,  G06F13/42 ,  G06F13/40

Abstract: A system includes a multi-conductor bus, a master device coupled to the multi-conductor bus, and at least one slave device coupled to the multi-conductor bus. The multi-conductor bus has a clock line and a data line. The master device is arranged to transmit an address configuration sequence, and the at least one slave device is arranged to configurably determine its own address based on at least one portion of the address configuration sequence. The at least one slave device has a physical address configuration input coupled to either a fixed voltage potential or a changing voltage potential. The at least one slave device is arranged with a first address during a pre-initialization state and arranged with a second address during a post-initialization state. During the post-initialization state, the first address and the second address are a same address when the address configuration sequence represents the first address and the first address and the second address are different addresses when the address configuration sequence does not represent the first address.

公开(公告)号：US20170300452A1

公开(公告)日：2017-10-19

申请号：US15639543

申请日：2017-06-30

Applicant: STMicroelectronics S.R.L.

Inventor： Marco Leo ,  Alessandra Maria Rizzo Piazza Roncoroni ,  Marco Castellano

IPC: G06F13/42 ,  G06F13/12 ,  G06F13/364 ,  G06F13/40

Abstract: An integrated data concentrator, so-called “sensor hub”, for a multi-sensor MEMS system, implements: a first interface module, for interfacing, in a normal operating mode, with a microprocessor through a first communication bus; and a second interface module, for interfacing, in the normal operating mode, with a plurality of sensors through a second communication bus; the sensor hub further implements a pass-through operating mode, distinct from the normal operating mode, in which it sets the microprocessor in direct communication with the sensors, through the first communication bus and the second communication bus. In particular, the sensor hub implements the direct pass-through operating mode in a totally digital manner.

公开(公告)号：US12135668B2

公开(公告)日：2024-11-05

申请号：US18056012

申请日：2022-11-16

Applicant: STMicroelectronics S.r.l.

Inventor： Marco Castellano ,  Francesco Bruni ,  Luca Gandolfi ,  Marco Leo

IPC: G06F3/00 ,  G06F13/40

Abstract: A processor includes a synchronous circuit including a plurality of processing stages, wherein each processing stage includes a selection data bus; and an asynchronous circuit coupled to each selection data bus, wherein the asynchronous circuit includes an asynchronous state machine whose states correspond to a process phase or a plurality of circuits, wherein the asynchronous circuit further includes a selectable delay circuit whose delay is determined by a present state of the asynchronous state machine, and wherein the asynchronous circuit is configured for generating a plurality of processing stage clock signals each having a selectable delay provided by the selectable delay circuit.

公开(公告)号：US20230259433A1

公开(公告)日：2023-08-17

申请号：US17670055

申请日：2022-02-11

Applicant: STMicroelectronics S.r.l.

Inventor： Enea Dimroci ,  Francesca Giacoma Mignemi ,  Roberta Priolo ,  Marco Leo ,  Francesco Battini

IPC: G06F11/26

CPC classification number: G06F11/26

Abstract: A method to test an asynchronous finite state machine for faults, the method including disabling state transitions out of a state of the asynchronous finite state machine and inputting test data to the AFSM to trigger a transition from the state to an expected state. The method further including enabling transitions out of the state of the asynchronous finite state machine, and determining whether the asynchronous finite state machine has performed a successful transition to the expected state.

公开(公告)号：US11112268B2

公开(公告)日：2021-09-07

申请号：US15688152

申请日：2017-08-28

Applicant: STMicroelectronics S.r.l.

Inventor： Marco Leo ,  Alessia Cagidiaco ,  Marco Catellano

IPC: G01C22/00 ,  G06N5/00 ,  G06N20/00 ,  G06F17/18

Abstract: Disclosed herein is a method including receiving multi-axis accelerometer data representing a potential step taken by a user of an electronic device. The method also includes determining whether the potential step represented by the multi-axis accelerometer data is a false. This determination is made by calculating statistical data from the multi-axis accelerometer data, and applying a decision tree to the statistical data to perform a cross correlation that determines whether the potential step is a false positive. If the potential step is not a false positive, a step detection process is performed to determine whether the potential step is a countable step and, if the potential step is found to be a countable step, a step counter is incremented.

公开(公告)号：US20160011981A1

公开(公告)日：2016-01-14

申请号：US14664630

申请日：2015-03-20

Applicant: STMicroelectronics S.r.l.

Inventor： Marco Leo ,  Paolo Rosingana ,  Marco Castellano

IPC: G06F12/08

CPC classification number: G06F12/0875 ,  G01D9/005 ,  G06F2212/1056 ,  G06F2212/451

Abstract: A plurality of sensors provide respective output data rates, with a first sensor that has a highest output data rate, while one or more other sensors have output data rates that are submultiples of the aforesaid highest output data rate. The data signals coming from the sensors are stored in a memory, e.g., a FIFO memory, by storing the data signals of the first sensor at the aforesaid highest output data rate, accompanying storage of the data signals coming from said first sensor with storage of the data signals coming from the sensors as supplied by said other sensors at the aforesaid submultiple output data rates, so that the data signals are stored in the memory according to a repeated pattern that is common to the various sensors.

Abstract translation: 多个传感器提供具有最高输出数据速率的第一传感器相应的输出数据速率，而一个或多个其它传感器具有作为上述最高输出数据速率的次数的输出数据速率。 来自传感器的数据信号通过将第一传感器的数据信号以上述最高输出数据速率存储在存储器（例如，FIFO存储器）中，伴随着来自所述第一传感器的数据信号的存储，存储 来自所述传感器的数据信号以所述其他传感器提供的上述多个输出数据速率，使得数据信号根据各种传感器共同的重复模式存储在存储器中。

公开(公告)号：US20150006778A1

公开(公告)日：2015-01-01

申请号：US14313769

申请日：2014-06-24

Applicant: STMicroelectronics S.r.l

Inventor： Marco Leo ,  Alessandra Maria Rizzo Piazza Roncoroni ,  Marco Castellano

IPC: G06F13/40

CPC classification number: G06F13/4286 ,  G06F13/124 ,  G06F13/364 ,  G06F13/385 ,  G06F13/4022 ,  G06F13/4027 ,  G06F2213/0016 ,  Y02D10/14 ,  Y02D10/151

Abstract: An integrated data concentrator, so-called “sensor hub”, for a multi-sensor MEMS system, implements: a first interface module, for interfacing, in a normal operating mode, with a microprocessor through a first communication bus; and a second interface module, for interfacing, in the normal operating mode, with a plurality of sensors through a second communication bus; the sensor hub further implements a pass-through operating mode, distinct from the normal operating mode, in which it sets the microprocessor in direct communication with the sensors, through the first communication bus and the second communication bus. In particular, the sensor hub implements the direct pass-through operating mode in a totally digital manner.

Abstract translation: 用于多传感器MEMS系统的集成数据集中器（即所谓的“传感器集线器”）实现：第一接口模块，用于以正常操作模式通过第一通信总线与微处理器进行接口; 以及第二接口模块，用于在正常操作模式下通过第二通信总线与多个传感器接口; 传感器集线器进一步实现与正常操作模式不同的直通操作模式，其中它通过第一通信总线和第二通信总线将微处理器设置为与传感器直接通信。 特别地，传感器集线器以完全数字的方式实现直接通过操作模式。

公开(公告)号：US10809062B2

公开(公告)日：2020-10-20

申请号：US15373282

申请日：2016-12-08

Applicant: STMICROELECTRONICS S.R.L.

Inventor： Marco Leo ,  Marco Castellano

IPC: G01P15/00 ,  G01C19/5776 ,  G01C25/00

Abstract: A MEMS inertial sensor device has a package and a gyroscopic sensor, an accelerometric sensor, and an ASIC electronic circuit integrated within the package. The ASIC is operatively coupled to the gyroscopic sensor and the accelerometric sensor for supplying at an output a gyroscopic signal indicative of an angular velocity and an acceleration signal indicative of an acceleration acting on the MEMS inertial sensor device. The ASIC is provided with a processing module, which may be of a purely hardware type, for processing jointly the gyroscopic signal and the accelerometric signal and determining a bias value present on the gyroscopic signal.

公开(公告)号：US20190063948A1

公开(公告)日：2019-02-28

申请号：US15688152

申请日：2017-08-28

Applicant: STMicroelectronics S.r.l.

Inventor： Marco Leo ,  Alessia Cagidiaco ,  Marco Catellano

IPC: G01C22/00

Abstract: Disclosed herein is a method including receiving multi-axis accelerometer data representing a potential step taken by a user of an electronic device. The method also includes determining whether the potential step represented by the multi-axis accelerometer data is a false. This determination is made by calculating statistical data from the multi-axis accelerometer data, and applying a decision tree to the statistical data to perform a cross correlation that determines whether the potential step is a false positive. If the potential step is not a false positive, a step detection process is performed to determine whether the potential step is a countable step and, if the potential step is found to be a countable step, a step counter is incremented.