Asynchronous controller for processing unit

    公开(公告)号:US12135668B2

    公开(公告)日:2024-11-05

    申请号:US18056012

    申请日:2022-11-16

    Abstract: A processor includes a synchronous circuit including a plurality of processing stages, wherein each processing stage includes a selection data bus; and an asynchronous circuit coupled to each selection data bus, wherein the asynchronous circuit includes an asynchronous state machine whose states correspond to a process phase or a plurality of circuits, wherein the asynchronous circuit further includes a selectable delay circuit whose delay is determined by a present state of the asynchronous state machine, and wherein the asynchronous circuit is configured for generating a plurality of processing stage clock signals each having a selectable delay provided by the selectable delay circuit.

    METHOD AND DEVICE FOR STORING DATA IN A MEMORY, CORRESPONDING APPARATUS AND COMPUTER PROGRAM PRODUCT
    2.
    发明申请
    METHOD AND DEVICE FOR STORING DATA IN A MEMORY, CORRESPONDING APPARATUS AND COMPUTER PROGRAM PRODUCT 有权
    用于在存储器中存储数据的方法和设备,相应的设备和计算机程序产品

    公开(公告)号:US20160011981A1

    公开(公告)日:2016-01-14

    申请号:US14664630

    申请日:2015-03-20

    CPC classification number: G06F12/0875 G01D9/005 G06F2212/1056 G06F2212/451

    Abstract: A plurality of sensors provide respective output data rates, with a first sensor that has a highest output data rate, while one or more other sensors have output data rates that are submultiples of the aforesaid highest output data rate. The data signals coming from the sensors are stored in a memory, e.g., a FIFO memory, by storing the data signals of the first sensor at the aforesaid highest output data rate, accompanying storage of the data signals coming from said first sensor with storage of the data signals coming from the sensors as supplied by said other sensors at the aforesaid submultiple output data rates, so that the data signals are stored in the memory according to a repeated pattern that is common to the various sensors.

    Abstract translation: 多个传感器提供具有最高输出数据速率的第一传感器相应的输出数据速率,而一个或多个其它传感器具有作为上述最高输出数据速率的次数的输出数据速率。 来自传感器的数据信号通过将第一传感器的数据信号以上述最高输出数据速率存储在存储器(例如,FIFO存储器)中,伴随着来自所述第一传感器的数据信号的存储,存储 来自所述传感器的数据信号以所述其他传感器提供的上述多个输出数据速率,使得数据信号根据各种传感器共同的重复模式存储在存储器中。

    INTEGRATED DATA CONCENTRATOR FOR MULTI-SENSOR MEMS SYSTEMS
    3.
    发明申请
    INTEGRATED DATA CONCENTRATOR FOR MULTI-SENSOR MEMS SYSTEMS 有权
    用于多传感器MEMS系统的集成数据集中器

    公开(公告)号:US20150006778A1

    公开(公告)日:2015-01-01

    申请号:US14313769

    申请日:2014-06-24

    Abstract: An integrated data concentrator, so-called “sensor hub”, for a multi-sensor MEMS system, implements: a first interface module, for interfacing, in a normal operating mode, with a microprocessor through a first communication bus; and a second interface module, for interfacing, in the normal operating mode, with a plurality of sensors through a second communication bus; the sensor hub further implements a pass-through operating mode, distinct from the normal operating mode, in which it sets the microprocessor in direct communication with the sensors, through the first communication bus and the second communication bus. In particular, the sensor hub implements the direct pass-through operating mode in a totally digital manner.

    Abstract translation: 用于多传感器MEMS系统的集成数据集中器(即所谓的“传感器集线器”)实现:第一接口模块,用于以正常操作模式通过第一通信总线与微处理器进行接口; 以及第二接口模块,用于在正常操作模式下通过第二通信总线与多个传感器接口; 传感器集线器进一步实现与正常操作模式不同的直通操作模式,其中它通过第一通信总线和第二通信总线将微处理器设置为与传感器直接通信。 特别地,传感器集线器以完全数字的方式实现直接通过操作模式。

    Dynamic definition of slave address in I2C protocol

    公开(公告)号:US10204066B2

    公开(公告)日:2019-02-12

    申请号:US15363932

    申请日:2016-11-29

    Abstract: A system includes a multi-conductor bus, a master device coupled to the multi-conductor bus, and at least one slave device coupled to the multi-conductor bus. The multi-conductor bus has a clock line and a data line. The master device is arranged to transmit an address configuration sequence, and the at least one slave device is arranged to configurably determine its own address based on at least one portion of the address configuration sequence. The at least one slave device has a physical address configuration input coupled to either a fixed voltage potential or a changing voltage potential. The at least one slave device is arranged with a first address during a pre-initialization state and arranged with a second address during a post-initialization state. During the post-initialization state, the first address and the second address are a same address when the address configuration sequence represents the first address and the first address and the second address are different addresses when the address configuration sequence does not represent the first address.

    INTEGRATED DATA CONCENTRATOR FOR MULTI-SENSOR MEMS SYSTEMS

    公开(公告)号:US20170300452A1

    公开(公告)日:2017-10-19

    申请号:US15639543

    申请日:2017-06-30

    Abstract: An integrated data concentrator, so-called “sensor hub”, for a multi-sensor MEMS system, implements: a first interface module, for interfacing, in a normal operating mode, with a microprocessor through a first communication bus; and a second interface module, for interfacing, in the normal operating mode, with a plurality of sensors through a second communication bus; the sensor hub further implements a pass-through operating mode, distinct from the normal operating mode, in which it sets the microprocessor in direct communication with the sensors, through the first communication bus and the second communication bus. In particular, the sensor hub implements the direct pass-through operating mode in a totally digital manner.

    METHOD AND SYSTEM FOR COMPENSATING SYSTEMATIC NON-LINEARITIES OF A SIGNAL PROVIDED BY A CAPACITIVE INERTIAL SENSOR
    6.
    发明申请
    METHOD AND SYSTEM FOR COMPENSATING SYSTEMATIC NON-LINEARITIES OF A SIGNAL PROVIDED BY A CAPACITIVE INERTIAL SENSOR 有权
    用于补偿由电容式惯性传感器提供的信号的系统非线性的方法和系统

    公开(公告)号:US20150323560A1

    公开(公告)日:2015-11-12

    申请号:US14672575

    申请日:2015-03-30

    CPC classification number: G01P21/00 G01C25/00 G01P15/125

    Abstract: A method for compensating non-linearities of a read signal generated by a variable-capacitance inertial sensor including a first fixed electrode and a second fixed electrode and a mobile electrode, which is spatially arranged between the first and second fixed electrodes and is capacitively coupled to the first and second fixed electrodes, said method comprising the steps of: acquiring the read signal; identifying a first linear component and at least one first nonlinear component of the read signal; a generating a compensated output signal by subtracting the first nonlinear component from the read signal.

    Abstract translation: 一种用于补偿由包括第一固定电极和第二固定电极和移动电极的可变电容惯性传感器产生的读取信号的非线性的方法,所述第一固定电极和第二固定电极和移动电极被空间地布置在第一和第二固定电极之间并且电容耦合到 所述第一和第二固定电极,所述方法包括以下步骤:获取读取信号; 识别所述读取信号的第一线性分量和至少一个第一非线性分量; 通过从读取信号中减去第一非线性分量来产生补偿输出信号。

    MEMS inertial sensor device with determination of the bias value of a gyroscope thereof and corresponding method

    公开(公告)号:US10809062B2

    公开(公告)日:2020-10-20

    申请号:US15373282

    申请日:2016-12-08

    Abstract: A MEMS inertial sensor device has a package and a gyroscopic sensor, an accelerometric sensor, and an ASIC electronic circuit integrated within the package. The ASIC is operatively coupled to the gyroscopic sensor and the accelerometric sensor for supplying at an output a gyroscopic signal indicative of an angular velocity and an acceleration signal indicative of an acceleration acting on the MEMS inertial sensor device. The ASIC is provided with a processing module, which may be of a purely hardware type, for processing jointly the gyroscopic signal and the accelerometric signal and determining a bias value present on the gyroscopic signal.

    Method of smart saving high-density data and memory device

    公开(公告)号:US10162551B2

    公开(公告)日:2018-12-25

    申请号:US15195352

    申请日:2016-06-28

    Abstract: A signal interface has a compression unit and a data memory. The compression unit is configured to input an input datum from signal data generated by at least one sensor and further configured to identify the presence or absence of at least one repetition condition in the input datum. If the presence of the at least one repetition condition of the input datum is identified, the compression unit encodes the input datum in a compressed way to generate a compressed datum and saves the compressed datum in the data memory. If the presence of the at least one repetition condition of the input datum is not identified, the compression unit saves the uncompressed input datum in the data memory.

    MEMS INERTIAL SENSOR DEVICE WITH DETERMINATION OF THE BIAS VALUE OF A GYROSCOPE THEROF AND CORRESPONDING METHOD

    公开(公告)号:US20170314923A1

    公开(公告)日:2017-11-02

    申请号:US15373282

    申请日:2016-12-08

    CPC classification number: G01C19/5776 G01C25/005

    Abstract: A MEMS inertial sensor device has a package and a gyroscopic sensor, an accelerometric sensor, and an ASIC electronic circuit integrated within the package. The ASIC is operatively coupled to the gyroscopic sensor and the accelerometric sensor for supplying at an output a gyroscopic signal indicative of an angular velocity and an acceleration signal indicative of an acceleration acting on the MEMS inertial sensor device. The ASIC is provided with a processing module, which may be of a purely hardware type, for processing jointly the gyroscopic signal and the accelerometric signal and determining a bias value present on the gyroscopic signal.

    Dynamic definition of slave address in I2C protocol

    公开(公告)号:US10459862B2

    公开(公告)日:2019-10-29

    申请号:US16219803

    申请日:2018-12-13

    Abstract: A system includes a multi-conductor bus, a master device coupled to the multi-conductor bus, and at least one slave device coupled to the multi-conductor bus. The multi-conductor bus has a clock line and a data line. The master device is arranged to transmit an address configuration sequence, and the at least one slave device is arranged to configurably determine its own address based on at least one portion of the address configuration sequence. The at least one slave device has a physical address configuration input coupled to either a fixed voltage potential or a changing voltage potential. The at least one slave device is arranged with a first address during a pre-initialization state and arranged with a second address during a post-initialization state. During the post-initialization state, the first address and the second address are a same address when the address configuration sequence represents the first address and the first address and the second address are different addresses when the address configuration sequence does not represent the first address.

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