公开(公告)号：US12224321B2

公开(公告)日：2025-02-11

申请号：US18532975

申请日：2023-12-07

Applicant: STMICROELECTRONICS S.r.l.

Inventor： Simone Rascuná ,  Mario Giuseppe Saggio

IPC: H01L29/16 ,  H01L29/66 ,  H01L29/872

Abstract: Merged-PiN-Schottky, MPS, device comprising: a substrate of SiC with a first conductivity; a drift layer of SiC with the first conductivity, on the substrate; an implanted region with a second conductivity, extending at a top surface of the drift layer to form a junction-barrier, JB, diode with the substrate; and a first electrical terminal in ohmic contact with the implanted region and in direct contact with the top surface to form a Schottky diode with the drift layer. The JB diode and the Schottky diode are alternated to each other along an axis: the JB diode has a minimum width parallel to the axis with a first value, and the Schottky diode has a maximum width parallel to the axis with a second value smaller than, or equal to, the first value. A breakdown voltage of the MPS device is greater than, or equal to, 115% of a maximum working voltage of the MPS device in an inhibition state.

公开(公告)号：US12125762B2

公开(公告)日：2024-10-22

申请号：US18052510

申请日：2022-11-03

Applicant: STMICROELECTRONICS S.r.l.

Inventor： Simone Rascuna' ,  Claudio Chibbaro ,  Alfio Guarnera ,  Mario Giuseppe Saggio ,  Francesco Lizio

IPC: H01L21/04 ,  H01L21/56 ,  H01L23/31 ,  H01L29/06 ,  H01L29/16 ,  H01L29/66 ,  H01L29/861 ,  H01L29/872

CPC classification number: H01L23/3171 ,  H01L21/045 ,  H01L21/56 ,  H01L29/1608

Abstract: An electronic power device includes a substrate of silicon carbide (SiC) having a front surface and a rear surface which lie in a horizontal plane and are opposite to one another along a vertical axis. The substrate includes an active area, provided in which are a number of doped regions, and an edge area, which is not active, distinct from and surrounding the active area. A dielectric region is arranged above the front surface, in at least the edge area. A passivation layer is arranged above the front surface of the substrate, and is in contact with the dielectric region in the edge area. The passivation layer includes at least one anchorage region that extends through the thickness of the dielectric region at the edge area, such as to define a mechanical anchorage for the passivation layer.

公开(公告)号：US11916066B2

公开(公告)日：2024-02-27

申请号：US17591534

申请日：2022-02-02

Applicant: STMICROELECTRONICS S.R.L.

Inventor： Mario Giuseppe Saggio ,  Simone Rascuná

IPC: H01L29/66 ,  H01L21/04 ,  H01L27/06 ,  H01L29/06 ,  H01L29/08 ,  H01L29/10 ,  H01L29/16 ,  H01L29/423 ,  H01L29/78 ,  H01L29/872

CPC classification number: H01L27/0629 ,  H01L21/046 ,  H01L29/0619 ,  H01L29/0696 ,  H01L29/0847 ,  H01L29/1095 ,  H01L29/1608 ,  H01L29/4238 ,  H01L29/66068 ,  H01L29/7806 ,  H01L29/872

Abstract: An integrated MOSFET device is formed in a body of silicon carbide and with a first type of conductivity. The body accommodates a first body region, with a second type of conductivity; a JFET region adjacent to the first body region; a first source region, with the first type of conductivity, extending into the interior of the first body region; an implanted structure, with the second type of conductivity, extending into the interior of the JFET region. An isolated gate structure lies partially over the first body region, the first source region and the JFET region. A first metallization layer extends over the first surface and forms, in direct contact with the implanted structure and with the JFET region, a JBS diode.

公开(公告)号：US11854809B2

公开(公告)日：2023-12-26

申请号：US18061795

申请日：2022-12-05

Applicant: STMICROELECTRONICS S.r.l.

Inventor： Edoardo Zanetti ,  Simone Rascuna' ,  Mario Giuseppe Saggio ,  Alfio Guarnera ,  Leonardo Fragapane ,  Cristina Tringali

IPC: H01L21/04 ,  H01L21/285 ,  H01L29/872 ,  H01L29/66 ,  H01L29/16 ,  H01L29/78 ,  H01L29/06

CPC classification number: H01L21/046 ,  H01L21/0495 ,  H01L21/28537 ,  H01L29/0619 ,  H01L29/0661 ,  H01L29/1608 ,  H01L29/6606 ,  H01L29/66068 ,  H01L29/66143 ,  H01L29/66734 ,  H01L29/7811 ,  H01L29/7813 ,  H01L29/872 ,  H01L29/8725

Abstract: A manufacturing method of an electronic device includes: forming a drift layer of an N type; forming a trench in the drift layer; forming an edge-termination structure alongside the trench by implanting dopant species of a P type; and forming a depression region between the trench and the edge-termination structure by digging the drift layer. The steps of forming the depression region and the trench are carried out at the same time. The step of forming the depression region comprises patterning the drift layer to form a structural connection with the edge-termination structure having a first slope, and the step of forming the trench comprises etching the drift layer to define side walls of the trench, which have a second slope steeper than the first slope.

公开(公告)号：US11545362B2

公开(公告)日：2023-01-03

申请号：US17244393

申请日：2021-04-29

Applicant: STMICROELECTRONICS S.r.l.

Inventor： Edoardo Zanetti ,  Simone Rascuna' ,  Mario Giuseppe Saggio ,  Alfio Guarnera ,  Leonardo Fragapane ,  Cristina Tringali

IPC: H01L29/16 ,  H01L21/04 ,  H01L21/285 ,  H01L29/872 ,  H01L29/66 ,  H01L29/78 ,  H01L29/06

Abstract: A manufacturing method of an electronic device includes: forming a drift layer of an N type; forming a trench in the drift layer; forming an edge-termination structure alongside the trench by implanting dopant species of a P type; and forming a depression region between the trench and the edge-termination structure by digging the drift layer. The steps of forming the depression region and the trench are carried out at the same time. The step of forming the depression region comprises patterning the drift layer to form a structural connection with the edge-termination structure having a first slope, and the step of forming the trench comprises etching the drift layer to define side walls of the trench, which have a second slope steeper than the first slope.

公开(公告)号：US09627472B2

公开(公告)日：2017-04-18

申请号：US14824813

申请日：2015-08-12

Applicant: STMICROELECTRONICS S.R.L.

Inventor： Mario Giuseppe Saggio ,  Domenico Murabito ,  Angelo Magri'

IPC: H01L27/088 ,  H01L29/06 ,  H01L29/78 ,  H01L29/08 ,  H01L29/739 ,  H01L29/10 ,  H01L29/66 ,  H01L29/417

CPC classification number: H01L29/0634 ,  H01L27/088 ,  H01L29/0649 ,  H01L29/086 ,  H01L29/1095 ,  H01L29/41766 ,  H01L29/66712 ,  H01L29/7395 ,  H01L29/7802 ,  H01L29/7811

Abstract: An embodiment of a structure for a high voltage device of the type which comprises at least a semiconductor substrate being covered by an epitaxial layer of a first type of conductivity, wherein a plurality of column structures are realized, which column structures comprises high aspect ratio deep trenches, said epitaxial layer being in turn covered by an active surface area wherein said high voltage device is realized, each of the column structures comprising at least an external portion being in turn realized by a silicon epitaxial layer of a second type of conductivity, opposed than said first type of conductivity and having a dopant charge which counterbalances the dopant charge being in said epitaxial layer outside said column structures, as well as a dielectric filling portion which is realized inside said external portion in order to completely fill said deep trench.

公开(公告)号：US08921211B2

公开(公告)日：2014-12-30

申请号：US14166522

申请日：2014-01-28

Applicant: STMicroelectronics S.r.l.

Inventor： Ferruccio Frisina ,  Mario Giuseppe Saggio ,  Angelo Magri′

IPC: H01L21/02 ,  H01L21/04 ,  H01L29/10 ,  H01L29/267 ,  H01L29/66 ,  H01L29/732 ,  H01L29/737 ,  H01L29/78 ,  H01L29/861 ,  H01L29/872 ,  H01L21/265 ,  H01L29/06 ,  H01L29/08 ,  H01L29/16

CPC classification number: H01L29/7806 ,  H01L21/02573 ,  H01L21/046 ,  H01L21/265 ,  H01L29/0619 ,  H01L29/0821 ,  H01L29/0878 ,  H01L29/1095 ,  H01L29/1608 ,  H01L29/165 ,  H01L29/267 ,  H01L29/66068 ,  H01L29/732 ,  H01L29/7371 ,  H01L29/7802 ,  H01L29/7804 ,  H01L29/7813 ,  H01L29/861 ,  H01L29/872

Abstract: An embodiment of a vertical-conduction integrated electronic device formed in a body of semiconductor material which includes: a substrate made of a first semiconductor material and with a first type of conductivity, the first semiconductor material having a first bandgap; an epitaxial region made of the first semiconductor material and with the first type of conductivity, which overlies the substrate and defines a first surface; and a first epitaxial layer made of a second semiconductor material, which overlies the first surface and is in direct contact with the epitaxial region, the second semiconductor material having a second bandgap narrower than the first bandgap. The body moreover includes a deep region of a second type of conductivity, extending underneath the first surface and within the epitaxial region.

Abstract translation: 形成在半导体材料体内的垂直导电集成电子器件的实施例包括：由第一半导体材料制成并具有第一导电类型的衬底，第一半导体材料具有第一带隙; 由第一半导体材料制成并且具有第一类型的导电性的外延区域，其覆盖在衬底上并限定第一表面; 以及由第二半导体材料制成的第一外延层，其覆盖在第一表面上并与外延区直接接触，第二半导体材料具有比第一带隙窄的第二带隙。 身体还包括延伸在第一表面下方和外延区域内的第二类导电性的深区域。

公开(公告)号：US12148824B2

公开(公告)日：2024-11-19

申请号：US17665398

申请日：2022-02-04

Applicant: STMicroelectronics S.r.l.

Inventor： Mario Giuseppe Saggio ,  Edoardo Zanetti

IPC: H01L29/78 ,  H01L21/70 ,  H01L29/06 ,  H01L29/10 ,  H01L29/16 ,  H01L29/423 ,  H01L29/66

Abstract: A MOSFET device comprising: a structural region, made of a semiconductor material having a first type of conductivity, which extends between a first side and a second side opposite to the first side along an axis; a body region, having a second type of conductivity opposite to the first type, which extends in the structural region starting from the first side; a source region, having the first type of conductivity, which extends in the body region starting from the first side; a gate region, which extends in the structural region starting from the first side, traversing entirely the body region; and a shielding region, having the second type of conductivity, which extends in the structural region between the gate region and the second side. The shielding region is an implanted region self-aligned, in top view, to the gate region.

公开(公告)号：US12094985B2

公开(公告)日：2024-09-17

申请号：US17818926

申请日：2022-08-10

Applicant: STMICROELECTRONICS S.R.L.

Inventor： Simone Rascuna′ ,  Mario Giuseppe Saggio

IPC: H01L29/16 ,  H01L29/06 ,  H01L29/20 ,  H01L29/45 ,  H01L29/47 ,  H01L29/66 ,  H01L29/872

CPC classification number: H01L29/872 ,  H01L29/0619 ,  H01L29/1608 ,  H01L29/2003 ,  H01L29/45 ,  H01L29/47 ,  H01L29/66143 ,  H01L29/66212

Abstract: A merged-PN-Schottky, MPS, diode includes an N substrate, an N-drift layer, a P-doped region in the drift layer, an ohmic contact on the P-doped region, a plurality of cells within the P-doped region and being portions of the drift layer where the P-doped region is absent, an anode metallization on the ohmic contact and on said cells, to form junction-barrier contacts and Schottky contacts respectively. The P-doped region has a grid-shaped layout separating from one another each cell and defining, together with the cells, an active area of the MPS diode. Each cell has a same geometry among quadrangular, quadrangular with rounded corners and circular; and the ohmic contact extends at the doped region with continuity along the grid-shaped layout.

公开(公告)号：US11869944B2

公开(公告)日：2024-01-09

申请号：US17374871

申请日：2021-07-13

Applicant: STMICROELECTRONICS S.R.L.

Inventor： Simone Rascuná ,  Mario Giuseppe Saggio

IPC: H01L29/16 ,  H01L29/66 ,  H01L29/872

CPC classification number: H01L29/1608 ,  H01L29/66136 ,  H01L29/66143 ,  H01L29/872

Abstract: Merged-PiN-Schottky, MPS, device comprising: a substrate of SiC with a first conductivity; a drift layer of SiC with the first conductivity, on the substrate; an implanted region with a second conductivity, extending at a top surface of the drift layer to form a junction-barrier, JB, diode with the substrate; and a first electrical terminal in ohmic contact with the implanted region and in direct contact with the top surface to form a Schottky diode with the drift layer. The JB diode and the Schottky diode are alternated to each other along an axis: the JB diode has a minimum width parallel to the axis with a first value, and the Schottky diode has a maximum width parallel to the axis with a second value smaller than, or equal to, the first value. A breakdown voltage of the MPS device is greater than, or equal to, 115% of a maximum working voltage of the MPS device in an inhibition state.