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公开(公告)号:US11362161B2
公开(公告)日:2022-06-14
申请号:US16823119
申请日:2020-03-18
Applicant: Samsung Display Co., Ltd.
Inventor: Young In Hwang , Ji Hye Kong , Suk Hoon Ku , Sung Wook Kim , Jin A Lee , Yun Sik Joo
IPC: H01L27/32 , G09G3/3233 , H01L29/786 , G09G3/20 , G09G3/3266 , G09G3/3275 , H01L27/12
Abstract: A display device includes pixels. Each of the pixels includes: a first transistor including a gate electrode connected to a first node, a first electrode connected to a second node, and a second electrode connected to a third node; a second transistor including a gate electrode connected to a first scan line, a first electrode connected to a data line, and a second electrode connected to the second node; a first sub-transistor including a gate electrode connected to the first scan line, a first electrode connected to the first node, and a second electrode connected to a fourth node; and a second sub-transistor including a gate electrode connected to the first scan line, a first electrode connected to the fourth node, and a second electrode connected to the third node. A channel width of the second sub-transistor is wider than a channel width of the first sub-transistor.
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公开(公告)号:US12133425B2
公开(公告)日:2024-10-29
申请号:US17398742
申请日:2021-08-10
Applicant: Samsung Display Co., Ltd.
Inventor: Eung Taek Kim , Kohei Ebisuno , Suk Hoon Ku , Jin Suk Lee , Jung Mi Choi , Young In Hwang , Tae Sik Kim , Jin Suk Seo , Hwang Sup Shin , Taek Geun Lee , Joo Hyeon Jo , Hong Jun Choi , Hee Yeon Kim , Na Lae Lee
IPC: G09G3/00 , H01L29/792 , H10K59/123 , H10K59/124 , H10K59/131 , G09G3/3208
CPC classification number: H10K59/124 , H01L29/792 , H10K59/123 , H10K59/131 , G09G3/3208
Abstract: A display device is provided. The display device includes a first substrate, a first charge trap layer disposed on the first substrate and including silicon nitride, a semiconductor layer disposed on the first charge trap layer and including a first active layer of a first transistor and a second active layer of a second transistor, and an organic light emitting element electrically connected to the first transistor, wherein a ratio of a content of a Si element to a content of an N element in the first charge trap layer is in a range of 1.6 to 2.5.
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公开(公告)号:US11793031B2
公开(公告)日:2023-10-17
申请号:US17831297
申请日:2022-06-02
Applicant: SAMSUNG DISPLAY CO., LTD.
Inventor: Young In Hwang , Ji Hye Kong , Suk Hoon Ku , Sung Wook Kim , Jin A Lee , Yun Sik Joo
IPC: H01L23/00 , H10K59/121 , G09G3/3233 , H01L29/786 , G09G3/20 , G09G3/3266 , G09G3/3275 , H01L27/12
CPC classification number: H10K59/1213 , G09G3/3233 , G09G3/2007 , G09G3/3266 , G09G3/3275 , G09G2300/0426 , G09G2300/0809 , G09G2310/08 , G09G2320/0233 , G09G2320/0247 , H01L27/1251 , H01L29/78696
Abstract: A display device includes pixels. Each of the pixels includes: a first transistor including a gate electrode connected to a first node, a first electrode connected to a second node, and a second electrode connected to a third node; a second transistor including a gate electrode connected to a first scan line, a first electrode connected to a data line, and a second electrode connected to the second node; a first sub-transistor including a gate electrode connected to the first scan line, a first electrode connected to the first node, and a second electrode connected to a fourth node; and a second sub-transistor including a gate electrode connected to the first scan line, a first electrode connected to the fourth node, and a second electrode connected to the third node. A channel width of the second sub-transistor is wider than a channel width of the first sub-transistor.
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公开(公告)号:US11730014B2
公开(公告)日:2023-08-15
申请号:US16797419
申请日:2020-02-21
Applicant: Samsung Display Co., Ltd.
Inventor: Hyangyul Kim , Sunhwa Kim , Heeseong Jeong , Suk Hoon Ku , Hyun-Gue Song , Dukjin Lee , Sang Min Yi
IPC: H01L51/52 , H10K50/86 , H10K50/842 , H10K59/122 , H10K59/131 , H10K59/121 , H10K102/00
CPC classification number: H10K50/86 , H10K50/8428 , H10K59/122 , H10K59/131 , H10K59/121 , H10K2102/351
Abstract: An electronic panel, includes: a base substrate including a front surface, a rear surface opposite the front surface, and a plurality of side surfaces connecting the front surface and the rear surface to each other; a pixel definition layer on the front surface of the base substrate and having a plurality of openings defined therein; a plurality of emitting elements in the openings; and a spacer on the pixel definition layer and spaced apart from the openings, wherein a thickness of the spacer is equal to or greater than a thickness of the pixel definition layer.
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公开(公告)号:US12277916B2
公开(公告)日:2025-04-15
申请号:US17493097
申请日:2021-10-04
Applicant: Samsung Display Co., Ltd.
Inventor: Jong-Woong Park , Suk Hoon Ku , Seok Jeong Song
IPC: G09G5/10 , G09G3/3275
Abstract: A data compensation circuit includes a reference frame memory device which stores reference frame data, an accumulated stress memory device which stores cumulative stress data for each of pixels, a stress data generating block which compares output image data with the reference frame data to generate stress data for each of the pixels, a memory control block which adds the stress data to the cumulative stress data to update the cumulative stress data and a compensating block which generates the output image data by generating afterimage compensation data for each of the pixels based on the cumulative stress data and compensating input image data based on the afterimage compensation data.
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公开(公告)号:US20160043233A1
公开(公告)日:2016-02-11
申请号:US14637224
申请日:2015-03-03
Applicant: SAMSUNG DISPLAY CO., LTD.
Inventor: Suk Hoon Ku , Hyunduck Cho
IPC: H01L29/786 , H01L29/423 , H01L29/36 , H01L21/3213 , H01L21/283 , H01L29/417 , H01L29/66 , H01L21/311
CPC classification number: H01L29/78609 , H01L29/41733 , H01L29/42384 , H01L29/66757 , H01L29/78618
Abstract: Provided are a thin film transistor (TFT) and a method of manufacturing the TFT. The TFT includes a substrate; a first conductive type semiconductor layer on the substrate and having a recess; second conductive type spacers at opposite side walls in the recess; a main semiconductor layer covering the first conductive type semiconductor layer and the second conductive type spacers and comprising a channel region and source and drain regions; a gate insulating layer on the main semiconductor layer; and a gate electrode on the gate insulating layer and corresponding to the recess.
Abstract translation: 提供薄膜晶体管(TFT)和制造TFT的方法。 TFT包括基板; 在所述基板上的第一导电型半导体层,并具有凹部; 在凹槽中相对侧壁上的第二导电型间隔物; 覆盖所述第一导电型半导体层和所述第二导电型间隔物的主半导体层,并且包括沟道区域和源极和漏极区域; 主半导体层上的栅极绝缘层; 以及栅极绝缘层上的对应于凹部的栅电极。
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7.
公开(公告)号:US20160027854A1
公开(公告)日:2016-01-28
申请号:US14709411
申请日:2015-05-11
Applicant: SAMSUNG DISPLAY CO., LTD.
Inventor: Suk Hoon Ku
IPC: H01L27/32 , H01L29/786
CPC classification number: H01L29/78606 , H01L27/1214 , H01L27/1218 , H01L29/78603 , H01L29/78666 , H01L29/78675 , H01L29/7869
Abstract: A thin film transistor includes: a semiconductor layer on a base substrate, and having a source region, a drain region, and a channel region; a gate insulating layer covering the semiconductor layer; a gate electrode on the gate insulating layer and overlapping the channel region; an interlayer insulating layer covering the gate electrode; a source electrode and a drain electrode on the interlayer insulating layer and respectively coupled to the source region and the drain region; and a temperature adjusting member configured to adjust a temperature of the channel region by heating the channel region.
Abstract translation: 薄膜晶体管包括:在基底基板上的半导体层,并具有源极区,漏极区和沟道区; 覆盖半导体层的栅极绝缘层; 栅极绝缘层上的栅电极,与沟道区重叠; 覆盖栅电极的层间绝缘层; 源极电极和漏极电极,分别耦合到源极区域和漏极区域; 以及温度调节部件,被配置为通过加热所述通道区域来调节所述通道区域的温度。
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公开(公告)号:US10020402B2
公开(公告)日:2018-07-10
申请号:US14637224
申请日:2015-03-03
Applicant: SAMSUNG DISPLAY CO., LTD.
Inventor: Suk Hoon Ku , Hyunduck Cho
IPC: H01L29/786 , H01L29/423 , H01L29/66 , H01L29/417
CPC classification number: H01L29/78609 , H01L29/41733 , H01L29/42384 , H01L29/66757 , H01L29/78618
Abstract: Provided are a thin film transistor (TFT) and a method of manufacturing the TFT. The TFT includes a substrate; a first conductive type semiconductor layer on the substrate and having a recess; second conductive type spacers at opposite side walls in the recess; a main semiconductor layer covering the first conductive type semiconductor layer and the second conductive type spacers and comprising a channel region and source and drain regions; a gate insulating layer on the main semiconductor layer; and a gate electrode on the gate insulating layer and corresponding to the recess.
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